A new common subexpression elimination algorithm with application in composite field AES S-box. - Ming Ming Wong; M. L. Dennis Wong (ISSPA, 2010)

A throughput maximised parallel architecture for 2D fast Discrete Pascal Transform. - Ming Ming Wong; M. L. Dennis Wong; Ismat Hijazin (Comput. Electr. Eng., 2010)

Composite field GF(((22)2)2) advanced encryption standard (AES) S-box with algebraic normal form representation in the subfield inversion. - Ming Ming Wong; M. L. Dennis Wong; Asoke K. Nandi; Ismat Hijazin (IET Circuits Devices Syst., 2011)

AES S-box using Fermat's Little Theorem for the highly constrained embedded devices. - Ming Ming Wong; M. L. Dennis Wong; Asoke K. Nandi; Ismat Hijazin (EUSIPCO, 2012)

Compact Multiplicative Inverter for Hardware Elliptic Curve Cryptosystem. - Ming Ming Wong; Mou Ling Dennis Wong; Ka Lok Man (NPC, 2012)

Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes. - Ming Ming Wong; M. L. Dennis Wong; Asoke K. Nandi; Ismat Hijazin (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Compact and low power AES block cipher using lightweight key expansion mechanism and optimal number of S-Boxes. - Jia Jun Tay; Ming Ming Wong; Ismat Hijazin (ISPACS, 2014)

New lightweight AES S-box using LFSR. - Ming Ming Wong; Mou Ling Dennis Wong (ISPACS, 2014)

Compact and short critical path finite field inverter for cryptographic S-box. - Ming Ming Wong; Mou Ling Dennis Wong; C. Zhang; Ismat Hijazin (DSP, 2015)

Survey of secure processors. - Suman Sau; Jawad Haj-Yahya; Ming Ming Wong; Kwok-Yan Lam; Anupam Chattopadhyay (SAMOS, 2017)

Stochastic Computing with Spiking Neural P Systems. - Ming Ming Wong; Mou Ling Dennis Wong (J. Univers. Comput. Sci., 2017)

SMARTS: secure memory assurance of RISC-V trusted SoC. - Ming Ming Wong; Jawad Haj-Yahya; Anupam Chattopadhyay (HASP@ISCA, 2018)

A New High Throughput and Area Efficient SHA-3 Implementation. - Ming Ming Wong; Jawad Haj-Yahya; Suman Sau; Anupam Chattopadhyay (ISCAS, 2018)

Construction of a Low Multiplicative Complexity GF (24) Inversion Circuit for Compact AES S-Box. - Jia Jun Tay; M. L. Dennis Wong; Ming Ming Wong; Cishen Zhang; Ismat Hijazin (TENCON, 2018)

Lightweight and High Performance SHA-256 using Architectural Folding and 4-2 Adder Compressor. - Ming Ming Wong; Vikramkumar Pudi; Anupam Chattopadhyay (VLSI-SoC, 2018)

A tree search algorithm for low multiplicative complexity logic design. - Jia Jun Tay; M. L. Dennis Wong; Ming Ming Wong; Cishen Zhang; Ismat Hijazin (Future Gener. Comput. Syst., 2018)

0.54 pJ/bit, 15Mb/s True Random Number Generator Using Probabilistic Delay Cell for Edge Computing Applications. - Fei Li 015; Ming Ming Wong; Aarthy Mani; Vishnu Paramasivam; Anh-Tuan Do (A-SSCC, 2019)

Lightweight Secure-Boot Architecture for RISC-V System-on-Chip. - Jawad Haj-Yahya; Ming Ming Wong; Vikramkumar Pudi; Shivam Bhasin; Anupam Chattopadhyay (ISQED, 2019)

Folded and Deterministic Stochastic MAC for High Accuracy and Hardware Efficient Convolution Function. - Ming Ming Wong; Anh-Tuan Do (SoCC, 2019)

Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGA. - Swagata Mandal; Sreetama Sarkar; Ming Ming Wong; Anupam Chattopadhyay; Amlan Chakrabarti (VLSID, 2019)

0.5V 4.8 pJ/SOP 0.93µW Leakage/core Neuromorphic Processor with Asynchronous NoC and Reconfigurable LIF Neuron. - Vishnu P. Nambiar; Junran Pu; Yun Kwan Lee; Aarthy Mani; Tao Luo 014; L. Yang; Eng-Kiat Koh; Ming Ming Wong; Fei Li 015; Wang Ling Goh; Anh Tuan Do (A-SSCC, 2020)

Ultra-Low Leakage, High Fan-Out Neuro Connection Map with TCAM-Based LUT, Localized Priority Encoder and Decoder-Less SRAM. - Aarthy Mani; Fei Li 015; Ming Ming Wong; Luo Tao; Liwei Yang; Vishnu Paramasivam; Anh Tuan Do (ISCAS, 2020)

Scalable Block-Based Spiking Neural Network Hardware with a Multiplierless Neuron Model. - Vishnu P. Nambiar; Eng-Kiat Koh; Junran Pu; Aarthy Mani; Ming Ming Wong; Li Fei; Wang Ling Goh; Anh Tuan Do (ISCAS, 2020)

A Backpropagation Extreme Learning Machine Approach to Fast Training Neural Network-Based Side-Channel Attack. - Xuyang Huang; Ming Ming Wong; Anh Tuan Do; Wang Ling Goh (AsianHOST, 2021)

A 2.1 pJ/SOP 40nm SNN Accelerator Featuring On-chip Transfer Learning using Delta STDP. - Ming Ming Wong; S. B. Shrestha; Vishnu P. Nambiar; Aarthy Mani; Yun Kwan Lee; Eng-Kiat Koh; W. Jiang; Kevin Tshun Chuan Chai; Anh-Tuan Do (ESSDERC, 2021)

A 25 TOPS/W High Power Efficiency Deterministic and Split Stochastic MAC (SC-MAC) Design. - Ming Ming Wong; Lu Chen; Anh Tuan Do (VLSI-SoC, 2021)

An Improved Deterministic Stochastic MAC (SC-MAC) for High Power Efficiency Design. - Ming Ming Wong; Lu Chen; Anh Tuan Do (VLSI-SoC (Selected Papers), 2021)

A 5.28-mm² 4.5-pJ/SOP Energy-Efficient Spiking Neural Network Hardware With Reconfigurable High Processing Speed Neuron Core and Congestion-Aware Router. - Junran Pu; Wang Ling Goh; Vishnu P. Nambiar; Ming Ming Wong; Anh Tuan Do (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Energy Efficient 0.5V 4.8pJ/SOP 0.93μW Leakage/Core Neuromorphic Processor Design. - Vishnu P. Nambiar; Junran Pu; Yun Kwan Lee; Aarthy Mani; Eng-Kiat Koh; Ming Ming Wong; Fei Li 015; Wang Ling Goh; Anh Tuan Do (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 1800μm2, 953Gbps/W AES Accelerator for IoT Applications in 40nm CMOS. - Jingjing Lan; Vishnu P. Nambiar; Ming Ming Wong; Fei Li 015; Yuan Gao 011; Kevin Tshun Chuan Chai; Anh Tuan Do (ISCAS, 2022)

Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency. - Liwei Yang; Huaipeng Zhang; Tao Luo 014; Chuping Qu; Myat Thu Linn Aung; Yingnan Cui; Jun Zhou 014; Ming Ming Wong; Junran Pu; Anh Tuan Do; Rick Siow Mong Goh; Weng-Fai Wong (Neurocomputing, 2022)

Corrigendum to "Coreset: Hierarchical neuromorphic computing supporting large-scale neural networks with improved resource efficiency" [Neurocomputing (2022) 128-140]. - Liwei Yang; Huaipeng Zhang; Tao Luo 014; Chuping Qu; Myat Thu Linn Aung; Yingnan Cui; Jun Zhou 014; Ming Ming Wong; Junran Pu; Anh Tuan Do; Rick Siow Mong Goh; Weng-Fai Wong (Neurocomputing, 2022)

1.7pJ/SOP Neuromorphic Processor with Integrated Partial Sum Routers for In-Network Computing. - Bo Wang 020; Ming Ming Wong; Dongrui Li; Yi Sheng Chong; Jun Zhou 014; Weng-Fai Wong; Li-Shiuan Peh; Aarthy Mani; Mohit Upadhyay; Ananta Narayanan Balaji; Anh Tuan Do (ISCAS, 2023)

1.63 pJ/SOP Neuromorphic Processor With Integrated Partial Sum Routers for In-Network Computing. - Dongrui Li; Ming Ming Wong; Yi Sheng Chong; Jun Zhou 014; Mohit Upadhyay; Ananta Narayanan Balaji; Aarthy Mani; Weng-Fai Wong; Li-Shiuan Peh; Anh Tuan Do; Bo Wang 020 (IEEE Trans. Very Large Scale Integr. Syst., 2024)