A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques. - Ming-Pin Chen; Lai-Fu Chen; Meng-Fan Chang; Shu-Meng Yang; Yao-Jen Kuo; Jui-Jen Wu; Mon-Shu Ho; Hsiu-Yun Su; Yuan-Hua Chu; Wen-Chin Wu; Tzu-Yi Yang; Hiroyuki Yamauchi (VLSIC, 2012)

A High Layer Scalability TSV-Based 3D-SRAM With Semi-Master-Slave Structure and Self-Timed Differential-TSV for High-Performance Universal-Memory-Capacity-Platforms. - Meng-Fan Chang; Chih-Sheng Lin; Wei-Cheng Wu; Ming-Pin Chen; Yen-Huei Chen; Zhe-Hui Lin; Shyh-Shyuan Sheu; Tzu-Kun Ku; Cha-Hsin Lin; Hiroyuki Yamauchi (IEEE J. Solid State Circuits, 2013)

Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells. - Shien-Chun Luo; Kuo-Chiang Chang; Ming-Pin Chen; Ching-Ji Huang; Yi-Fang Chiu; Po-Hsun Chen; Liang-Chia Cheng; Chih-Wei Liu; Yuan-Hua Chu (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Read circuits for resistive memory (ReRAM) and memristor-based nonvolatile Logics. - Meng-Fan Chang; Albert Lee; Chien-Chen Lin; Mon-Shu Ho; Ping-Cheng Chen; Chia-Chen Kuo; Ming-Pin Chen; Pei-Ling Tseng; Tzu-Kun Ku; Chien-Fu Chen; Kai-Shin Li; Jia-Min Shieh (ASP-DAC, 2015)