A 20Gb/s Duobinary Transceiver in 90nm CMOS. - Jri Lee; Ming-Shuan Chen; Huaide Wang (ISSCC, 2008)

Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary, PAM4, and NRZ Data. - Jri Lee; Ming-Shuan Chen; Huaide Wang (IEEE J. Solid State Circuits, 2008)

A 40Gb/s TX and RX chip set in 65nm CMOS. - Ming-Shuan Chen; Yu-Nan Shih; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (ISSCC, 2011)

A low-power highly multiplexed parallel PRBS generator. - Ming-Shuan Chen; Chih-Kong Ken Yang (CICC, 2012)

A Fully-Integrated 40-Gb/s Transceiver in 65-nm CMOS Technology. - Ming-Shuan Chen; Yu-Nan Shih; Chen-Lun Lin; Hao-Wei Hung; Jri Lee (IEEE J. Solid State Circuits, 2012)

A 32-to-48Gb/s serializing transmitter using multiphase sampling in 65nm CMOS. - Amr Amin Hafez; Ming-Shuan Chen; Chih-Kong Ken Yang (ISSCC, 2013)

A 0.1-1.5 GHz 8-bit Inverter-Based Digital-to-Phase Converter Using Harmonic Rejection. - Ming-Shuan Chen; Amr Amin Hafez; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2013)

A 50-64 Gb/s serializing transmitter with a 4-tap, LC-ladder-filter-based FFE in 65-nm CMOS. - Ming-Shuan Chen; Chih-Kong Ken Yang (CICC, 2014)

A low-PDP and low-area repeater using passive CTLE for on-chip interconnects. - Ming-Shuan Chen; Mau-Chung Frank Chang; Chih-Kong Ken Yang (VLSIC, 2015)

A 50-64 Gb/s Serializing Transmitter With a 4-Tap, LC-Ladder-Filter-Based FFE in 65 nm CMOS Technology. - Ming-Shuan Chen; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2015)

A 32-48 Gb/s Serializing Transmitter Using Multiphase Serialization in 65 nm CMOS Technology. - Amr Amin Hafez; Ming-Shuan Chen; Chih-Kong Ken Yang (IEEE J. Solid State Circuits, 2015)