Partition methodology for the final adder in a tree-structure parallel multiplier generator. - Tso-Bing Juang; Jeng-Hsiun Jan; Ming-Yu Tsai; Shen-Fu Hsiao (APCCAS (1), 2002)

Automatic Integration of Inter-Enterprise Processes with Hierarchical Broker Framework. - Shun-Fa Chang; Li-Chen Fu; Ming-Yu Tsai (ICEIS (4), 2004)

Para-CORDIC: parallel CORDIC rotation algorithm. - Tso-Bing Juang; Shen-Fu Hsiao; Ming-Yu Tsai (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Automatic Negotiation with Mediated Agents in E-commerce Marketplace. - Ming-Yu Tsai; Li-Chen Fu; Ta-Chiun Chou (EEE, 2005)

An efficient pass-transistor-logic synthesizer using multiplexers and inverters only. - Shen-Fu Hsiao; Ming-Yu Tsai; Ming-Chih Chen; Chia-Sheng Wen (ISCAS (3), 2005)

A Cell-Driven Multiplier Generator with Delay Optimization of Partial Products Compression and an Efficient Partition Technique for the Final Addition. - Tso-Bing Juang; Shen-Fu Hsiao; Ming-Yu Tsai; Jenq-Shiun Jan (IEICE Trans. Inf. Syst., 2005)

An Automatic Cache Generator Based on Content-Addressable Memory. - Shen-Fu Hsiao; Sze-Yun Lin; Tze-Chong Cheng; Ming-Yu Tsai (APCCAS, 2006)

Efficient Pass-Transistor-Logic Synthesis for Sequential Circuits. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (APCCAS, 2006)

Novel Memory Organization and Circuit Designs for Efficient Data Access in Applications of 3D Graphics and Multimedia Coding. - Shen-Fu Hsiao; Yo-Chi Chen; Ming-Yu Tsai; Tze-Chong Cheng (MTDT, 2006)

Efficient designs of flaoting-point CORDIC rotation and vectoring operations. - Shen-Fu Hsiao; Hsin-Mau Lee; Yen-Chun Cheng; Ming-Yu Tsai (APCCAS, 2008)

Area oriented pass-transistor logic synthesis using buffer elimination and layout compaction. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (ISCAS, 2008)

Corrections to "VLSI Design of Diminished-One Modulo 2n + 1 Adder Using Circular Carry Selection" [Sep 08 897-901]. - Tso-Bing Juang; Ming-Yu Tsai; Chin-Chieh Chiu (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Low Area/Power Synthesis Using Hybrid Pass Transistor/CMOS Logic Cells in Standard Cell-Based Design Environment. - Shen-Fu Hsiao; Ming-Yu Tsai; Chia-Sheng Wen (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Improved Area-Efficient Weighted Modulo 2n + 1 Adder Design With Simple Correction Schemes. - Tso-Bing Juang; Chin-Chieh Chiu; Ming-Yu Tsai (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A Virtual Cluster Head Election Scheme for Energy-Efficient Routing in Wireless Sensor Networks. - Ming-Yu Tsai; Yaw-Chung Chen (FiCloud, 2015)

Image Recognition Technology for Abnormal Capsule Detection. - Chuin-Mu Wang; Shao Wei Chu; Yen-Ching Wu; Jia-Xian Jian; Ming-Yu Tsai; Meng-Fen Huang (BCD, 2023)