An energy-efficient circuit technique for single event transient noise-tolerance. - Ming Zhang 017; Naresh R. Shanbhag (ISCAS (1), 2005)

Logic soft errors: a major barrier to robust platform design. - Subhasish Mitra; Ming Zhang 017; T. M. Mak; Norbert Seifert; Victor Zia; Kee Sup Kim (ITC, 2005)

Subhasish Mitra, Norbert Seifert, Ming Zhang, Quan Shi, Kee Sup Kim. - Subhasish Mitra; Norbert Seifert; Ming Zhang 017; Quan Shi; Kee Sup Kim (Computer, 2005)

Combinational Logic Soft Error Correction. - Subhasish Mitra; Ming Zhang 017; Saad Waqas; Norbert Seifert; Balkaran S. Gill; Kee Sup Kim (ITC, 2006)

Soft Error Resilient System Design through Error Correction. - Subhasish Mitra; Ming Zhang 017; Norbert Seifert; T. M. Mak; Kee Sup Kim (VLSI-SoC (Selected Papers), 2006)

Soft-Error-Rate-Analysis (SERA) Methodology. - Ming Zhang 017; Naresh R. Shanbhag (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Dual-Sampling Skewed CMOS Design for Soft-Error Tolerance. - Ming Zhang 017; Naresh R. Shanbhag (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Sequential Element Design With Built-In Soft Error Resilience. - Ming Zhang 017; Subhasish Mitra; T. M. Mak; Norbert Seifert; Nicholas J. Wang; Quan Shi; Kee Sup Kim; Naresh R. Shanbhag; Sanjay J. Patel (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Analysis and Design of Soft-Error Tolerant Circuits - Ming Zhang 017 (2006)

Design for Resilience to Soft Errors and Variations. - Ming Zhang 017; T. M. Mak; James W. Tschanz; Kee Sup Kim; Norbert Seifert; Davia Lu (IOLTS, 2007)

Hierarchical Test Compression for SoC Designs. - Kee Sup Kim; Ming Zhang 017 (IEEE Des. Test Comput., 2008)