A 12-bit SAR ADC with a reversible VCM-based capacitor switching scheme. - Mingchao Jian; Jiwei Zheng; Xiangjian Kong; Meng Yuan; Chunhua Zhang; Chunbing Guo; Bo Sun (Microelectron. J., 2022)

A Dual-Core Quad_Mode VCO with Reconfigurable Magnetic Coupling Mode and Negative-Resistive Mode Switch. - Xiangjian Kong; Ding Qiu; Mingchao Jian; Chunbing Guo; Kai Xu (ASICON, 2023)

Design and optimization of a new CMOS high-speed H-H neuron. - Chunbing Guo; Yicheng Xiao; Mingchao Jian; Jianlin Zhao; Bo Sun (Microelectron. J., 2023)

A 1-V 9.6-GHz charge-pump PLL with low RMS-integrated jitter. - Ding Qiu; Xiangjian Kong; Mingchao Jian; Jiwei Zheng; Chunbing Guo (Microelectron. J., 2023)

A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement. - Xiangjian Kong; Kai Xu; Robert Bogdan Staszewski; Mingchao Jian; Chunbing Guo (VLSI Technology and Circuits, 2024)

A 73-dB-SNDR 2nd-Order Noise-Shaping SAR With a Low-Noise Time-Domain Comparator. - Mingchao Jian; Jiwei Zheng; Xiangjian Kong; Bo Sun; Chunbing Guo (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 2-MHz BW 93.2-dB SFDR 2nd-Order Hybrid EF-CIFF Noise Shaping SAR ADC. - Mingjie Li; Mingchao Jian; Huanlin Xie; Jiajun Yang; Jiawei Tian; Bo Sun; Chunbing Guo (Microelectron. J., 2025)

A time-interleaved 2b/Cycle SAR ADC with sign-inversion method for timing-skew calibration. - Jiawei Tian; Mingchao Jian; Huanlin Xie; Mingjie Li; Jiajun Yang; Chunbing Guo (Microelectron. J., 2025)

A 24-kHz bandwidth 94.8-dB-SNDR discrete-time dynamic zoom ADC with analog-domain combine. - Zhenyu Wang; Huanlin Xie; Mingchao Jian; Mingtao Hu; Bo Sun; Chunbing Guo (Microelectron. J., 2025)

A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique. - Xiangjian Kong; Kai Xu; Huanlin Xie; Mingchao Jian; Hao Lian; Robert Bogdan Staszewski; Chunbing Guo (IEEE J. Solid State Circuits, 2025)