Parallel Scheduling Self-attention Mechanism: Generalization and Optimization. - Mingfei Yu; Masahiro Fujita (CoRR, 2020)

A Decomposition-Based Synthesis Algorithm for Sparse Matrix-Vector Multiplication in Parallel Communication Structure. - Mingfei Yu; Ruitao Gao; Masahiro Fujita (ASP-DAC, 2021)

Logic Synthesis for Generalization and Learning Addition. - Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita (DATE, 2021)

Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. - Shubham Rai; Walter Lau Neto; Yukio Miyasaka; Xinpei Zhang; Mingfei Yu; Qingyang Yi; Masahiro Fujita; Guilherme B. Manske; Matheus F. Pontes; Leomar S. da Rosa; Marilton S. de Aguiar; Paulo F. Butzen; et al. (DATE, 2021)

Loop Closure Detection by Using Global and Local Features With Photometric and Viewpoint Invariance. - Mingfei Yu; Lei Zhang 021; Wufan Wang; Hua Huang 001 (IEEE Trans. Image Process., 2021)

Low-Precision Quantization Techniques for Hardware-Implementation-Friendly BERT Models. - Xinpei Zhang; Yi Ding; Mingfei Yu; Shin-ichi O'Uchi; Masahiro Fujita (ISQED, 2022)

Parallel Scheduling Attention Mechanism: Generalization and Optimization. - Mingfei Yu; Yukio Miyasaka; Masahiro Fujita (IPSJ Trans. Syst. LSI Des. Methodol., 2022)

Generating Lower-Cost Garbled Circuits: Logic Synthesis Can Help. - Mingfei Yu; Giovanni De Micheli (HOST, 2023)

Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled Circuits. - Mingfei Yu; Giovanni De Micheli (ICCAD, 2023)

SCP-SLAM: Accelerating DynaSLAM With Static Confidence Propagation. - Mingfei Yu; Lei Zhang 021; Wu-Fan Wang; Jia-Hui Wang (VR, 2023)

Garbled Circuits Reimagined: Logic Synthesis Unleashes Efficient Secure Computation. - Mingfei Yu; Dewmini Sudara Marakkalage; Giovanni De Micheli (Cryptogr., 2023)

Unleashing the Power of T1-cells in SFQ Arithmetic Circuits. - Rassul Bairamkulov; Mingfei Yu; Giovanni De Micheli (DAC, 2024)

Technology-Aware Logic Synthesis for Superconducting Electronics. - Rassul Bairamkulov; Siang-Yun Lee; Alessandro Tempia Calvino; Dewmini Sudara Marakkalage; Mingfei Yu; Giovanni De Micheli (DATE, 2024)

RareLS: Rarity-Reducing Logic Synthesis for Mitigating Hardware Trojan Threats. - Chang Meng; Mingfei Yu; Hanyu Wang; Wayne P. Burleson; Giovanni De Micheli (ICCAD, 2024)

On the Synthesis of High-performance Homomorphic Boolean Circuits. - Mingfei Yu; Sergiu Carpov; Alessandro Tempia Calvino; Giovanni De Micheli (WAHC@CCS, 2024)

Expediting Homomorphic Computation via Multiplicative Complexity-aware Multiplicative Depth Minimization. - Mingfei Yu; Giovanni De Micheli (IACR Cryptol. ePrint Arch., 2024)

Back-end-aware Fault-tolerant Quantum Oracle Synthesis. - Mingfei Yu; Alessandro Tempia Calvino; Mathias Soeken; Giovanni De Micheli (ASP-DAC, 2025)

Cut Tracing with E-Graphs for Boolean FHE Circuit Synthesis. - Julien de Castelnau; Mingfei Yu; Giovanni De Micheli (CoRR, 2025)