Memory-efficient interconnect optimization. - Minghorng Lai; D. F. Wong 001 (ASP-DAC, 2001)

Slicing tree is a complete floorplan representation. - Minghorng Lai; D. F. Wong 001 (DATE, 2001)

Maze routing with buffer insertion and wiresizing. - Minghorng Lai; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Floorplanning with power supply noise avoidance. - Hung-Ming Chen; Li-Da Huang; I-Min Liu; Minghorng Lai; D. F. Wong 001 (ASP-DAC, 2003)

Maze routing with buffer insertion under transition time constraints. - Li-Da Huang; Minghorng Lai; Martin D. F. Wong; Youxin Gao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003)