A power reduction technique for wideband common gate low noise amplifers. - Minghua Wang; Minglei Zhang; Xiaohua Fan; Yu Liu 030 (MWSCAS, 2014)

High-speed low-power decimation filter for wideband Delta-Sigma ADC. - Yi Xie; Minglei Zhang; Baoyue Wei; Xiaohua Fan (MWSCAS, 2014)

An energy-efficient SAR ADC using a single-phase clocked dynamic comparator with energy and speed enhanced technique. - Minglei Zhang; Xiaohua Fan (IEICE Electron. Express, 2017)

A 0.8-1.2 V 10-50 MS/s 13-bit Subranging Pipelined-SAR ADC Using a Temperature-Insensitive Time-Based Amplifier. - Minglei Zhang; Kyoohyun Noh; Xiaohua Fan; Edgar Sánchez-Sinencio (IEEE J. Solid State Circuits, 2017)

A Financial Embedded Vector Model and Its Applications to Time Series Forecasting. - Yanfeng Sun; Minglei Zhang; Si Chen; Xiaohu Shi (Int. J. Comput. Commun. Control, 2018)

A 13.56-MHz CMOS Active Rectifier With a Voltage Mode Switched-Offset Comparator for Implantable Medical Devices. - Kyoohyun Noh; Judy M. Amanor-Boadu; Minglei Zhang; Edgar Sánchez-Sinencio (IEEE Trans. Very Large Scale Integr. Syst., 2018)

A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier. - Wenning Jiang; Yan Zhu 001; Minglei Zhang; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2019)

A 0.6V 13b 20MS/s Two-Step TDC-Assisted SAR ADC with PVT Tracking and Speed-Enhanced Techniques. - Minglei Zhang; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (ISSCC, 2019)

A 0.6-V 13-bit 20-MS/s Two-Step TDC-Assisted SAR ADC With PVT Tracking and Speed-Enhanced Techniques. - Minglei Zhang; Chi-Hang Chan; Yan Zhu 001; Rui Paulo Martins (IEEE J. Solid State Circuits, 2019)

A Unified Amplifier-Based CC-CV Linear Charger for Energy-Constrained Low-Power Applications. - Kyoohyun Noh; Minglei Zhang; Edgar Sánchez-Sinencio (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 1-MHz-Bandwidth Gm-C-Based Quadrature Bandpass Sigma-Delta Modulator Achieving -153.7-dBFS/Hz NSD With Background Calibration. - Minglei Zhang; Qingsong Cai; Zhong Yang; Xiaoyun Jia; Xiaohua Fan (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

16.2 A 4× Interleaved 10GS/s 8b Time-Domain ADC with 16× Interpolation-Based Inter-Stage Gain Achieving >37.5dB SNDR at 18GHz Input. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2020)

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier. - Wenning Jiang; Yan Zhu 001; Minglei Zhang; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With <1.5-ps Uncalibrated Quantization Steps. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (IEEE J. Solid State Circuits, 2020)

Background Calibration of Bit Weights in Pipelined-SAR ADCs Using Paired Comparators. - Jie Sun 020; Minglei Zhang; Lei Qiu 002; Jianhui Wu 001; Weiqiang Liu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 4-bit Mixed-Signal MAC Array with Swing Enhancement and Local Kernel Memory. - Wei-Han Yu; Massimo Giordano; Rohan Doshi; Minglei Zhang; Pui-In Mak; Rui Paulo Martins; Boris Murmann (MWSCAS, 2021)

A 20GS/s 8b Time-Interleaved Time-Domain ADC with Input-Independent Background Timing Skew Calibration. - Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Circuits, 2021)

Forecasting the Trend of COVID-19 Considering the Impacts of Public Health Interventions: An Application of FGM and Buffer Level. - Kai Lisa Lo; Minglei Zhang; Yanhui Chen; Jinhong Jackson Mi (J. Heal. Informatics Res., 2021)

A Double-Mode Sparse Compute-In-Memory Macro with Reconfigurable Single and Dual Layer Computation. - Yuanzhe Zhao; Minglei Zhang; Pengyu He; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (CICC, 2023)

Intelligent electronic information equipment maintenance and testing system based on general test instruments. - Qiang Gao; Minglei Zhang; Deyi Sun (ICBASE, 2023)

A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A Single-Channel 2.6GS/s 10b Dynamic Pipelined ADC with Time-Assisted Residue Generation Scheme Achieving Intrinsic PVT Robustness. - Junyan Hao; Minglei Zhang; Yanbo Zhang; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 2x-lnterleaved 9b 2.8G8S/s 5b/cycle SAR ADC with Linearized Configurable V2T Buffer Achieving >50dB SNDR at 3GHz Input. - Hongzhi Zhao; Minglei Zhang; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (ISSCC, 2023)

A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors. - Minglei Zhang; Yuefeng Cao; Yan Zhu 001; Chi-Hang Chan; Rui Paulo Martins (VLSI Technology and Circuits, 2023)

A 52.5-dB 2× Time-Interleaved 2.8-GS/s SAR ADC With 5-bit/Cycle Time-Domain Quantization and a Compact Signal DAC. - Hongzhi Zhao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

The Race for the Extra Pico Second without Losing the Decibel: A Partial-Review of Single-Channel Energy-Efficient High-Speed Nyquist ADCs. - Chi-Hang Chan; Minglei Zhang; Yuefeng Cao; Honazhi Zhao; Rui Paulo Martins; Yan Zhu 001 (CICC, 2024)

A 28nm 314.6TLFOPS/W Reconfigurable Floating-Point Analog Compute-In-Memory Macro with Exponent Approximation and Two-Stage Sharing TD-ADC. - Pengyu He; Yuanzhe Zhao; Heng Xie; Yang Wang 089; Shouyi Yin; Li Li 064; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2024)

A PVT-Robust 8b 20GS/s Time-Interleaved SAR ADC with Quantization-Embedded Current-Mode Buffer and Differ-Based Dither Timing Skew Calibration. - Wei Zhang; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (CICC, 2024)

Integration of EEG signal features for diagnosing alcohol use disorders. - Meng Xiao; Shasha Zhong; Yandan Xu; Minglei Zhang; Xiaofan Wang (ISAIMS, 2024)

22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2024)

6.8 A 256×192-Pixel 30fps Automotive Direct Time-of-Flight LiDAR Using 8× Current-Integrating-Based TIA, Hybrid Pulse Position/Width Converter, and Intensity/CNN-Guided 3D Inpainting. - Chaorui Zou; Yaozhong Ou; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (ISSCC, 2024)

Ha-gnn: a novel graph neural network based on hyperbolic attention. - Hongbo Qu; Yurong Song; Minglei Zhang; Guo-Ping Jiang; Ruqi Li; Bo Song (Neural Comput. Appl., 2024)

FLEX-CIM: A Flexible Kernel Size 1-GHz 181.6-TOPS/W 25.63-TOPS/mm2 Analog Compute-in-Memory Macro. - Yuzhao Fu; Wei-Han Yu; Ka-Fai Un; Chi-Hang Chan; Yan Zhu 001; Minglei Zhang; Rui Paulo Martins; Pui-In Mak (IEEE J. Solid State Circuits, 2024)

A 256 × 192 -Pixel Direct Time-of-Flight LiDAR Receiver With a Current-Integrating-Based AFE Supporting 240-m-Range Imaging. - Chaorui Zou; Yaozhong Ou; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (IEEE J. Solid State Circuits, 2024)

A 12-GS/s 12-b 4× Time-Interleaved ADC Using Input-Independent Timing Skew Calibration With Global Dither Injection and Linearized Input Buffer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2024)

A 28nm Value-Wise Hybrid-Domain Compute-in-Memory Macro with Heterogeneous Memory Fabric and Asynchronous Sparsity Manager. - Yuanzhe Zhao; Yang Wang 089; Yuheng Wang; Heng Xie; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Shouyi Yin; Minglei Zhang (CICC, 2025)

A Reconfigurable 0.69-1.02nJ/Classification Biomedical AI Processor for Intelligent Health Monitoring Devices. - Yuanzhe Zhao; Yuheng Wang; Zijian Wang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2025)

A One-Shot Floating-Point Compute-in-Memory Macro Featuring PVT Robustness and Mismatch Tolerance for Edge LLMs. - Yuanzhe Zhao; Heng Xie; Zijian Wang; Chunlin Tian; Li Li 064; Yan Zhu 001; R. P. Martins; Chi-Hang Chan; Minglei Zhang (CICC, 2025)

24.4 A 10b 3GS/s Time-Domain ADC with Mutually Exclusive Metastability Correction and Wide Common-Mode Input. - Zijian Liu; Minglei Zhang; Wei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

24.5 A 72GS/s 9b Time-Interleaved Pipeline-SAR ADC Achieving 55.3/49.3dB SFDR at 20GHz/Nyquist Inputs in 16nm FinFET. - Yannan Zhang; Minglei Zhang; Zehang Wu; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

24.3: A PVT-Robust 2× Interleaved 2.2GS/s ADC with Gated-CCRO-Based Quantizer Shared Across Channels and Steps Achieving >4.5GHz ERBW. - Junlin Zhong; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (ISSCC, 2025)

CLONE: Customizing LLMs for Efficient Latency-Aware Inference at the Edge. - Chunlin Tian; Xinpeng Qin; Kahou Tam; Li Li 064; Zijian Wang; Yuanzhe Zhao; Minglei Zhang; Chengzhong Xu 001 (USENIX ATC, 2025)

A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer. - Yuefeng Cao; Minglei Zhang; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2025)

SRPO: A Cross-Domain Implementation of Large-Scale Reinforcement Learning on LLM. - Xiaojiang Zhang; Jinghui Wang; Zifei Cheng; Wenhao Zhuang; Zheng Lin; Minglei Zhang; Shaojie Wang; Yinghan Cui; Chao Wang; Junyi Peng; Shimiao Jiang; Shiqi Kuang; et al. (CoRR, 2025)

An Intrinsically PVT Robust 10-bit 2.6-GS/s Dynamic Pipelined ADC With Dual-Path Time-Assisted Residue Generation Scheme. - Junyan Hao; Minglei Zhang; Zijian Liu; Yanbo Zhang; Shubin Liu; Zhangming Zhu; Yan Zhu 001; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2025)

SeamlessFlow: A Trainer Agent Isolation RL Framework Achieving Bubble-Free Pipelines via Tag Scheduling. - Jinghui Wang; Shaojie Wang; Yinghan Cui; Xuxing Chen; Chao Wang; Xiaojiang Zhang; Minglei Zhang; Jiarong Zhang; Wenhao Zhuang; Yuchen Cao; Wankang Bao; Haimo Li; et al. (CoRR, 2025)