High performance transistors based on two dimensional materials. - Mingqiang Huang; Xiong Xiong; Tiaoyang Li; Yanqing Wu (ASICON, 2017)

Winograd Algorithm for AdderNet. - Wenshuo Li; Hanting Chen; Mingqiang Huang; Xinghao Chen 001; Chunjing Xu; Yunhe Wang 001 (ICML, 2021)

Hardware-Friendly Stochastic and Adaptive Learning in Memristor Convolutional Neural Networks. - Wei Zhang; Lunshuai Pan; Xuelong Yan; Guangchao Zhao; Hong Chen; Xingli Wang; Beng Kang Tay; Gaokuo Zhong; Jiangyu Li; Mingqiang Huang (Adv. Intell. Syst., 2021)

AdderNet and its Minimalist Hardware Design for Energy-Efficient Artificial Intelligence. - Yunhe Wang 001; Mingqiang Huang; Kai Han 002; Hanting Chen; Wei Zhang 196; Chunjing Xu; Dacheng Tao (CoRR, 2021)

A General-Purpose and Configurable Planar Data Processor for Energy-Efficient Pooling Computation. - Lunshuai Pan; Peng Xue; Hongxing Li; Litao Sun; Mingqiang Huang (AICAS, 2022)

A Precision-Scalable Energy-Efficient Bit-Split-and-Combination Vector Systolic Accelerator for NAS-Optimized DNNs on Edge. - Kai Li 024; Junzhuo Zhou; Yuhang Wang; Junyi Luo; Zhengke Yang; Shuxin Yang; Wei Mao 002; Mingqiang Huang; Hao Yu 001 (DATE, 2022)

Dual-Line-Systolic Array for High Performance CNN Accelerator. - Peng Xue; Lunshuai Pan; Litao Sun; Mingqiang Huang (FCCM, 2022)

A High Throughput Multi-bit-width 3D Systolic Accelerator for NAS Optimized Deep Neural Networks on FPGA. - Mingqiang Huang; Yucen Liu; Quan Cheng; Shuxin Yang; Kai Li 024; Junyi Luo; Zhengke Yang; Qiufeng Li; Hao Yu 001; Changhai Man (FPGA, 2022)

An Energy-Efficient Mixed-Bit CNN Accelerator With Column Parallel Readout for ReRAM-Based In-Memory Computing. - Dingbang Liu; Haoxiang Zhou; Wei Mao 002; Jun Liu; Yuliang Han; Changhai Man; Qiuping Wu; Zhiru Guo; Mingqiang Huang; Shaobo Luo; Mingsong Lv; Quan Chen 007; et al. (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

A High Performance Multi-Bit-Width Booth Vector Systolic Accelerator for NAS Optimized Deep Learning Neural Networks. - Mingqiang Huang; Yucen Liu; Changhai Man; Kai Li 024; Quan Cheng; Wei Mao 002; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

An Energy-Efficient Mixed-Bitwidth Systolic Accelerator for NAS-Optimized Deep Neural Networks. - Wei Mao 002; Liuyao Dai; Kai Li 024; Quan Cheng; Yuhang Wang; Laimin Du; Shaobo Luo; Mingqiang Huang; Hao Yu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Group Vectored Absolute-Value-Subtraction Cell Array for the Efficient Acceleration of AdderNet. - Jiahao Chen; Wanbo Hu; Wenling Ma; Zhilin Zhang; Mingqiang Huang (AICAS, 2023)

RRAM-Based Precision-Scaleable Computing-In-Memory Scheme and Its Error Correction Approach. - Wenling Ma; Lianzheng Li; Ziye Li; Guangchao Zhao; Xiaojing Long; Mingqiang Huang (AICAS, 2023)

Multi-bit-width CNN Accelerator with Systolic-in-Systolic Dataflow and Single DSP Multiple Multiplication Scheme. - Mingqiang Huang; Yucen Liu; Sixiao Huang; Kai Li 024; Qiuping Wu; Hao Yu 001 (FPGA, 2023)

A Low-Power Sparse Convolutional Neural Network Accelerator With Pre-Encoding Radix-4 Booth Multiplier. - Quan Cheng; Liuyao Dai; Mingqiang Huang; Ao Shen; Wei Mao 002; Masanori Hashimoto; Hao Yu 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Reliability Exploration of System-on-Chip With Multi-Bit-Width Accelerator for Multi-Precision Deep Neural Networks. - Quan Cheng; Mingqiang Huang; Changhai Man; Ao Shen; Liuyao Dai; Hao Yu 001; Masanori Hashimoto (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An Integer-Only and Group-Vector Systolic Accelerator for Efficiently Mapping Vision Transformer on Edge. - Mingqiang Huang; Junyi Luo; Chenchen Ding; Zikun Wei; Sixiao Huang; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 13-34 TOPS/W Edge-AI Processor Featuring Booth-Value-Confined Accelerator, Near-Memory Computing, and Contiguity-Aware Mapping. - Quan Cheng; Longyang Lin; Mingqiang Huang; Qiufeng Li; Zhengke Yang; Liuyao Dai; Hao Yu 001; Yu-Jen Chen; Yiyu Shi 001; Masanori Hashimoto (A-SSCC, 2024)

A 29.12 TOPS/W and 1.13 TOPS/mm2 NAS-Optimized Mixed-Precision DNN Accelerator with Vector Split- and-Combination Systolic in 28nm CMOS. - Kai Li 024; Hantao Huang; Mingqiang Huang; Chenchen Ding; Longyang Lin; Liebing Ni; Hao Yu 001 (CICC, 2024)

LAMPS: A Layer-wised Mixed-Precision-and-Sparsity Accelerator for NAS-Optimized CNNs on FPGA. - Shuxin Yang; Chenchen Ding; Mingqiang Huang; Kai Li 024; Chenghao Li 010; Zikun Wei; Sixiao Huang; Jingyao Dong; Liuyang Zhang; Hao Yu 001 (FCCM, 2024)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. - Mingqiang Huang; Ao Shen; Kai Li 024; Haoxiang Peng; Boyu Li; Hao Yu 001 (CoRR, 2024)

Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms. - Guangchao Zhao; Zhiwei Zeng; Xingli Wang; Abdelrahman G. Qoutb; Philippe Coquet; Eby G. Friedman; Beng Kang Tay; Mingqiang Huang (IEEE Trans. Emerg. Top. Comput., 2024)

An MLA-LLM Hardware Acceleration with Tensor-Train Decomposition on Group Vector Systolic Accelerator. - Sixiao Huang; Tintin Wang; Keyao Jiang; Ao Shen; Kai Li; Ang Li; Mingqiang Huang; Hao Yu (ASAP, 2025)

A 22nm Resource-Frugal Hyper-Heterogeneous Multi-Modal System-on-Chip Towards In-Orbit Computing. - Quan Cheng; Qiufeng Li; Weirong Dong; Mingtao Zhang; Ruilin Zhang; Mingqiang Huang; Hao Yu 001; Yiyu Shi 001; Hiromitsu Awano; Takashi Sato 001; Longyang Lin; Masanori Hashimoto (CICC, 2025)

A Tensor-Train Decomposition based Compression of LLMs on Group Vector Systolic Accelerator. - Sixiao Huang; Tintin Wang; Ang Li; Ao Shen; Kai Li; Keyao Jiang; Mingqiang Huang; Hao Yu (CoRR, 2025)

EdgeLLM: A Highly Efficient CPU-FPGA Heterogeneous Edge Accelerator for Large Language Models. - Mingqiang Huang; Ao Shen; Kai Li 024; Haoxiang Peng; Boyu Li; Yupeng Su; Hao Yu 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

High Efficiency Multiply-Accumulator Using Ternary Logic and Ternary Approximate Algorithm. - Wanting Wen; Guangchao Zhao; Wanbo Hu; Ziye Li; Xingli Wang; Eby G. Friedman; Beng Kang Tay; Shaolin Ke; Mingqiang Huang (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)