9.3 A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping. - Jiaxin Liu; Xing Wang; Zijie Gao; Mingtao Zhan; Xiyuan Tang; Nan Sun 001 (ISSCC, 2020)

A 2.75-to-75.9TOPS/W Computing-in-Memory NN Processor Supporting Set-Associate Block-Wise Zero Skipping and Ping-Pong CIM with Simultaneous Computation and Weight Updating. - Jinshan Yue; Xiaoyu Feng; Yifan He 003; Yuxuan Huang; Yipeng Wang 009; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hung; et al. (ISSCC, 2021)

A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping. - Jiaxin Liu; Xing Wang; Zijie Gao; Mingtao Zhan; Xiyuan Tang; Chen-Kai Hsu; Nan Sun 001 (IEEE J. Solid State Circuits, 2021)

A 0.014mm2 10kHz-BW Zoom-Incremental-Counting ADC Achieving 103dB SNDR and 100dB Full-Scale CMRR. - Lu Jie 001; Mingtao Zhan; Xiyuan Tang; Nan Sun 001 (ISSCC, 2022)

A 0.004mm2 200MS/S Pipelined SAR ADC with kT/C Noise Cancellation and Robust Ring-Amp. - Mingtao Zhan; Lu Jie 001; Xiyuan Tang; Nan Sun 001 (ISSCC, 2022)

An 80.2-to-89.1dB-SNDR 24k-to-200kHz-BW VCO-Based Synthesized ?S ADC with 105dB SFDR in 28-nm CMOS. - Yi Zhong; Mingtao Zhan; Wei Wang; Xiyuan Tang; Lu Jie 001; Nan Sun 001 (CICC, 2023)

A 150kHz-BW 15-ENOB Incremental Zoom ADC with Skipped Sampling and Single Buffer Embedded Noise-Shaping SAR Quantizer. - Zongnan Wang; Lu Jie 001; Zichen Kong; Mingtao Zhan; Yi Zhong; Yuan Wang 001; Xiyuan Tang (ISSCC, 2023)

A 10mW 10-ENOB 1GS/s Ring-Amp-Based Pipelined TI-SAR ADC with Split MDAC and Switched Reference Decoupling Capacitor. - Mingtao Zhan; Lu Jie 001; Nan Sun 001 (ISSCC, 2023)

A 5.6-89.9TOPS/W Heterogeneous Computing-in-Memory SoC with High-Utilization Producer-Consumer Architecture and High-Frequency Read-Free CIM Macro. - Jinshan Yue; Mingtao Zhan; Zi Wang; Yifan He 002; Yaolei Li; Songming Yu; Wenyu Sun; Lu Jie 001; Chunmeng Dou; Xueqing Li 002; Nan Sun 001; Huazhong Yang; et al. (VLSI Technology and Circuits, 2023)

An In-Memory-Computing Charge-Domain Ternary CNN Classifier. - Xiangxing Yang; Keren Zhu 001; Xiyuan Tang; Meizhi Wang; Mingtao Zhan; Nanshu Lu; Jaydeep P. Kulkarni; David Z. Pan; Yongpan Liu; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

A 10-mW 10-ENoB 1-GS/s Ring-Amp-Based Pipelined TI-SAR ADC With Split MDAC and Switched Reference Decoupling Capacitor. - Mingtao Zhan; Lu Jie 001; Yi Zhong; Nan Sun 001 (IEEE J. Solid State Circuits, 2023)

An Energy-Efficient Computing-in-Memory NN Processor With Set-Associate Blockwise Sparsity and Ping-Pong Weight Update. - Jinshan Yue; Yongpan Liu; Xiaoyu Feng; Yifan He 002; Jingyu Wang 004; Zhe Yuan; Mingtao Zhan; Jiaxin Liu; Jian-Wei Su; Yen-Lin Chung; Ping-Chun Wu; Li-Yang Hong; et al. (IEEE J. Solid State Circuits, 2024)

A 0.004-mm2 200-MS/s Pipelined SAR ADC With kT/C Noise Cancellation and Robust Ring-Amp. - Mingtao Zhan; Lu Jie 001; Xiyuan Tang; Yi Zhong; Nan Sun 001 (IEEE J. Solid State Circuits, 2024)

An 8b 10GS/s 2-Channel Time-Interleaved Pipelined ADC with Concurrent Residue Transfer and Quantization, and Automatic Buffer Power Gating. - Yunsong Tao; Mingtao Zhan; Mingyang Gu; Xiyu He; Yuxuan He; Zhishuai Zhang; Yi Zhong; Lu Jie 001; Nan Sun 001 (ISSCC, 2025)

3.4: A CMOS Operational Amplifier Achieving ±5.8µV 3σ Offset and ±88nV/°C 3σ Offset Drift Using an on-Chip Heater-Based Self-Trimming Technique. - Aodong Zhang; Mingtao Zhan; Mengying Chen; Yi Zhong; Lu Jie 001; Nan Sun 001; Qinwen Fan (ISSCC, 2025)