TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. - Mingyang Kou; Jiangyuan Gu; Shaojun Wei; Hailong Yao; Shouyi Yin (DAC, 2020)

Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits. - Mingyang Kou; Pei-Yi Cheng; Jun Zeng 001; Tsung-Yi Ho; Kazuyoshi Takagi; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

GEML: GNN-based efficient mapping method for large loop applications on CGRA. - Mingyang Kou; Jun Zeng; Boxiao Han; Fei Xu; Jiangyuan Gu; Hailong Yao (DAC, 2022)

KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference. - Jun Zeng; Mingyang Kou; Hailong Yao (ACM Great Lakes Symposium on VLSI, 2022)

NeuroSchedule: A Novel Effective GNN-based Scheduling Method for High-level Synthesis. - Jun Zeng; Mingyang Kou; Hailong Yao (NeurIPS, 2022)

TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. - Mingyang Kou; Jiangyuan Gu; Hailong Yao; Shaojun Wei; Shouyi Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography. - Chengkai Wang; Weiqing Ji; Mingyang Kou; Zhiyang Chen 006; Fei Li; Hailong Yao (CoRR, 2024)

VAER: Via-Aware Escape Routing for Chiplet Interconnection. - Haochang Tian; Weiqing Ji; Mingyang Kou; Chengkai Wang; Fei Li; Hailong Yao (ACM Great Lakes Symposium on VLSI, 2025)