FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface. - Mingyen Lee; Wenjun Tang; Bowen Xue; Juejian Wu; Mingyuan Ma; Yu Wang 002; Yongpan Liu; Deliang Fan; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (ISLPED, 2020)

YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chip. - Yiming Chen; Guodong Yin; Zhanhong Tan; Mingyen Lee; Zekun Yang; Yongpan Liu; Huazhong Yang; Kaisheng Ma; Xueqing Li 002 (DAC, 2022)

Hidden-ROM: A Compute-in-ROM Architecture to Deploy Large-Scale Neural Networks on Chip with Flexible and Scalable Post-Fabrication Task Transfer Capability. - Yiming Chen; Guodong Yin; Mingyen Lee; Wenjun Tang; Zekun Yang; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ICCAD, 2022)

FAST: A Fully-Concurrent Access Technique to All SRAM Rows for Enhanced Speed and Energy Efficiency in Data-Intensive Applications. - Yiming Chen; Yushen Fu; Mingyen Lee; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (CoRR, 2022)

GRAPHIC: GatheR-And-Process in Highly parallel with In-SSD Compression Architecture in Very Large-Scale Graph. - Yiming Chen; Guohao Dai; Mufeng Zhou; Mingyen Lee; Nagadastagiri Challapalle; Guodong Yin; Zekun Yang; Yongpan Liu; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (CoRR, 2022)

A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface. - Guodong Yin; Mufeng Zhou; Yiming Chen; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (CoRR, 2022)

Victor: A Variation-resilient Approach Using Cell-Clustered Charge-domain computing for High-density High-throughput MLC CiM. - Mingyen Lee; Wenjun Tang; Yiming Chen; Juejian Wu; Hongtao Zhong; Yixin Xu 001; Yongpan Liu; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (DAC, 2023)

FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge. - Wenjun Tang; Mingyen Lee; Juejian Wu; Yixin Xu 001; Yao Yu; Yongpan Liu; Kai Ni 004; Yu Wang 002; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

FAST: A Fully-Concurrent Access SRAM Topology for High Row-Wise Parallelism Applications Based on Dynamic Shift Operations. - Yiming Chen; Yushen Fu; Mingyen Lee; Sumitha George; Yongpan Liu; Vijaykrishnan Narayanan; Huazhong Yang; Xueqing Li 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

SAMBA: Single-ADC Multi-Bit Accumulation Compute-in-Memory Using Nonlinearity- Compensated Fully Parallel Analog Adder Tree. - Yiming Chen; Guodong Yin; Mufeng Zhou; Wenjun Tang; Zekun Yang; Mingyen Lee; Xirui Du; Jinshan Yue; Jiaxin Liu; Huazhong Yang; Yongpan Liu; Xueqing Li 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

ZEBRA: A Zero-Bit Robust-Accumulation Compute-In-Memory Approach for Neural Network Acceleration Utilizing Different Bitwise Patterns. - Yiming Chen; Guodong Yin; Hongtao Zhong; Mingyen Lee; Huazhong Yang; Sumitha George; Vijaykrishnan Narayanan; Xueqing Li 002 (ASPDAC, 2024)

A 28nm 166.9 TOPS/W x Mb/mm2 DRAM-Free QLC Compute-in-ROM Macro Supporting High Task-Level Inference Energy Efficiency for Tiny AI Edge Devices. - Ling-An Cheong; Chen Wang; Mufeng Zhou; Tianyu Liao; Mingyen Lee; Yue Ke; Wenjun Tang; Yiming Chen; Xirui Du; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (A-SSCC, 2024)

A 28nm 8928Kb/mm2-Weight-Density Hybrid SRAM/ROM Compute-in-Memory Architecture Reducing >95% Weight Loading from DRAM. - Guodong Yin; Yiming Chen; Mingyen Lee; Xirui Du; Yue Ke; Wenjun Tang; Zhonghao Chen; Mufeng Zhou; Jinshan Yue; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (CICC, 2024)

GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility. - Yiming Chen; Mingyen Lee; Guohao Dai; Mufeng Zhou; Nagadastagiri Challapalle; Tianyi Wang; Yao Yu; Yongpan Liu; Yu Wang 002; Huazhong Yang; Vijaykrishnan Narayanan; Xueqing Li 002 (IEEE Trans. Emerg. Top. Comput., 2024)

Cramming More Weight Data Onto Compute-in-Memory Macros for High Task-Level Energy Efficiency Using Custom ROM With 3984-kb/mm2 Density in 65-nm CMOS. - Guodong Yin; Yiming Chen; Mufeng Zhou; Wenjun Tang; Mingyen Lee; Zekun Yang; Tianyu Liao; Xirui Du; Vijaykrishnan Narayanan; Huazhong Yang; Hongyang Jia; Yongpan Liu; et al. (IEEE J. Solid State Circuits, 2024)

DCiROM: A Fully Digital Compute-in-ROM Design Approach to High Energy Efficiency of DNN Inference at Task Level. - Tianyi Yu; Tianyu Liao; Mufeng Zhou; Xiaotian Chu; Guodong Yin; Mingyen Lee; Yongpan Liu; Huazhong Yang; Xueqing Li 002 (ASP-DAC, 2025)