A Spatial and Temporal Locality-Aware Adaptive Cache Design With Network Optimization for Tiled Many-Core Architectures. - Mingyu Wang 003; Zhaolin Li (IEEE Trans. Very Large Scale Integr. Syst., 2017)

3D-NWA: A Nested-Winograd Accelerator for 3D CNNs. - Huafeng Ye; Huipeng Deng; Jian Wang 080; Mingyu Wang 003; Zhiyi Yu (ICTA, 2022)

LWSDP: Locality-Aware Warp Scheduling and Dynamic Data Prefetching Co-design in the Per-SM Private Cache of GPGPUs. - Wangguang Wang; Mingyu Wang 003; Yicong Zhang; Yukun Wei; Zhiyi Yu (ICPADS, 2023)

A Scalable Deadlock-Free Static Routing Algorithm for Chiplet-Based Systems. - Xiaoran Zhang; Mingyu Wang 003; Yicong Zhang; Tao Lu; Zhiyi Yu (ICPADS, 2023)

A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips. - Yangzhan Mai; Mingyu Wang 003; Chuanghao Zhang; Baiqing Zhong; Zhiyi Yu (ISCAS, 2023)

A Digital SRAM Computing-in-Memory Design Utilizing Activation Unstructured Sparsity for High-Efficient DNN Inference. - Baiqing Zhong; Mingyu Wang 003; Chuanghao Zhang; Yangzhan Mai; Xiaojie Li; Zhiyi Yu (ISVLSI, 2023)

MAICC : A Lightweight Many-core Architecture with In-Cache Computing for Multi-DNN Parallel Inference. - Renhao Fan; Yikai Cui; Qilin Chen; Mingyu Wang 003; Youhui Zhang; Weimin Zheng; Zhaolin Li (MICRO, 2023)

A High-Density and Reconfigurable SRAM-Based Digital Compute-In-Memory Macro for Low-Power AI Chips. - Chuanghao Zhang; Mingyu Wang 003; Yangzhan Mai; Chengcheng Tang; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

TensorCache: Reconstructing Memory Architecture With SRAM-Based In-Cache Computing for Efficient Tensor Computations in GPGPUs. - Yicong Zhang; Mingyu Wang 003; Yangzhan Mai; Zhiyi Yu (IEEE Trans. Very Large Scale Integr. Syst., 2023)

BafSP: Co-Design of Compute SRAM and Bit-Aware Data Flip Mitigation with In-Memory Sparsity Detection for SpMM. - Xiaojie Li; Mingyu Wang 003; Yangzhan Mai; Yicong Zhang; Baiqing Zhong; Zhiyi Yu (ISVLSI, 2024)

DAW-DMR: Divergence-Aware Warped DMR with Full Error Detection for GPGPU s. - Yukun Wei; Mingyu Wang 003; Haiqiu Huang; Wangguang Wang; Zhiyi Yu (ISVLSI, 2024)

Atomic Cache: Enabling Efficient Fine-Grained Synchronization with Relaxed Memory Consistency on GPGPUs Through In-Cache Atomic Operations. - Yicong Zhang; Mingyu Wang 003; Wangguang Wang; Yangzhan Mai; Haiqiu Huang; Zhiyi Yu (MICRO, 2024)

MagiCache: A Virtual In-Cache Computing Engine. - Renhao Fan; Yikai Cui; Weike Li; Mingyu Wang 003; Zhaolin Li (ISCA, 2025)

CINOC: Computing in Network-On-Chip With Tiled Many-Core Architectures for Large-Scale General Matrix Multiplications. - Yao Qin; Mingyu Wang 003; Jiahua Yan; Tao Lu; Zhiyi Yu (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Hybrid CAM-SRAM Processing-in-Memory Architecture With Feature Level Sparsity for Attention Mechanisms. - Haiqiu Huang; Mingyu Wang 003; Xiaojie Li; Baiqing Zhong; Zeqi Yang; Tao Lu; Yicong Zhang; Zhiyi Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2025)