DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. - Minh Quang Do; Lars Bengtsson; Per Larsson-Edefors (Applied Informatics, 2003)

Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. - Minh Quang Do; Per Larsson-Edefors; Lars Bengtsson (PATMOS, 2004)

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. - Minh Quang Do; Mindaugas Drazdziulis; Per Larsson-Edefors; Lars Bengtsson (ISQED, 2006)

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. - Minh Quang Do; Per Larsson-Edefors; Mindaugas Drazdziulis (DSD, 2007)

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. - Minh Quang Do; Mindaugas Drazdziulis; Per Larsson-Edefors; Lars Bengtsson (ISQED, 2007)