Simulation of Quantum-Dot Structures in Si/SiO2. - Minhan Chen; Wolfgang Porod (VLSI Design, 1998)

A Low-Ripple Resistor-Less Hybrid Loop Filter based PLL in 3nm FinFET. - Ping Lu; Charlie Boecker; Bupesh Pandita; Minhan Chen; Sheethal Nayak (ISCAS, 2022)

An adaptive wide-range Time-to-Digital Converter with flexible resolution for DPLL applications. - Ping Lu; Minhan Chen; Shaishav Desai (MWSCAS, 2022)

Reference Clock Jitter Immunity by Accurate DPLL Bandwidth Control in a Multiple-link Die-to-Die Interface. - Ping Lu; Bupesh Pandita; Minhan Chen (MWSCAS, 2023)

A Reduced-Fractional-Spur DPLL Based on Cyclic Single-Delay-Pair Vernier TDC. - Ping Lu; Minhan Chen; Shaishav Desai (ISCAS, 2024)