Towards Memory-Efficient Streaming Processing with Counter-Cascading Sketching on FPGA. - Minjin Tang; Mei Wen; Junzhong Shen; Xiaolei Zhao; Chunyuan Zhang (DAC, 2020)

Scalable FPGA-based Architecture for High-Performance Per-Flow Traffic Measurement. - Junzhong Shen; Mei Wen; Minjin Tang; Xiaolei Zhao; Chunyuan Zhang (FPGA, 2020)

Optimized HybridSketch: More Efficient with Analysis and Algorithm. - Xiaolei Zhao; Mei Wen; Minjin Tang; Qun Huang 001; Chunyuan Zhang (ICA3PP (1), 2020)

HybridSketch: A Memory-centric Precise Approach for Flow Measurement. - Xiaolei Zhao; Mei Wen; Minjin Tang; Qun Huang 001; Chunyuan Zhang (ICC, 2020)

SAI: Self-Adjusting Incremental Quantile Estimation for Sparse Training of Neural Networks on Hardware Accelerators. - Jianchao Yang; Mei Wen; Minjin Tang; Junzhong Shen; Chunyuan Zhang (HPCC/DSS/SmartCity/DependSys, 2021)

MZ Core: An Enhanced Matrix Acceleration Engine for HPC/ AI Applications. - Yasong Cao; Mei Wen; Junzhong Shen; Sheng Liu 001; Zhi Wang; Minjin Tang; Yahao Fang; Jianchao Yang; Renyu Yang; Yuhan Kang; Jiawei Fei (HPCC/DSS/SmartCity/DependSys, 2022)

BP-Im2col: Implicit Im2col Supporting AI Backpropagation on Systolic Arrays. - Jianchao Yang; Mei Wen; Junzhong Shen; Yasong Cao; Minjin Tang; Renyu Yang; Jiawei Fei; Chunyuan Zhang (ICCD, 2022)

Mentha: Enabling Sparse-Packing Computation on Systolic Arrays. - Minjin Tang; Mei Wen; Yasong Cao; Junzhong Shen; Jianchao Yang; Jiawei Fei; Yang Guo 003; Sheng Liu 001 (ICPP, 2022)

Releasing the Potential of Tensor Core for Unstructured SpMM using Tiled-CSR Format. - Zeyu Xue; Mei Wen; Zhaoyun Chen; Yang Shi 008; Minjin Tang; Jianchao Yang; Zhongdi Luo (ICCD, 2023)

MSA2: An Efficient Sparsity-Aware Accelerator for Matrix Multiplication with Multi-core Systolic Arrays. - Minjin Tang; Mei Wen; Junzhong Shen; Jingkui Yang; Zeyu Xue; Zili Shao (ICA3PP (3), 2024)

SparSynergy: Unlocking Flexible and Efficient DNN Acceleration Through Multi-Level Sparsity. - Jingkui Yang; Mei Wen; Junzhong Shen; Jianchao Yang; Yasong Cao; Jun He; Minjin Tang; Zhaoyun Chen; Yang Shi 008 (DATE, 2025)

SPSA: Exploring Sparse-Packing Computation on Systolic Arrays From Scratch. - Minjin Tang; Mei Wen; Jianchao Yang; Zeyu Xue; Junzhong Shen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)