Minkyu Kim

Orcid: 0000-0001-7084-9163

Affiliations:
  • Arizona State University, School of Electrical, Computer and Energy Engineering, Tempe, USA


According to our database1, Minkyu Kim authored at least 16 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2023
PIMCA: A Programmable In-Memory Computing Accelerator for Energy-Efficient DNN Inference.
IEEE J. Solid State Circuits, May, 2023

2021
An Energy-Efficient Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access.
IEEE J. Solid State Circuits, 2021

PIMCA: A 3.4-Mb Programmable In-Memory Computing Accelerator in 28nm for On-Chip DNN Inference.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021

2020
Vesti: Energy-Efficient In-Memory Computing Accelerator for Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Deep Convolutional Neural Network Accelerator Featuring Conditional Computing and Low External Memory Access.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
Energy-Efficient ASIC Accelerators for Machine/Deep Learning Algorithms.
PhD thesis, 2019

A Real-Time 17-Scale Object Detection Accelerator With Adaptive 2000-Stage Classification in 65 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A 1.06- $\mu$ W Smart ECG Processor in 65-nm CMOS for Real-Time Biometric Authentication and Personal Cardiac Monitoring.
IEEE J. Solid State Circuits, 2019

Inference engine benchmarking across technological platforms from CMOS to RRAM.
Proceedings of the International Symposium on Memory Systems, 2019

Vesti: An In-Memory Computing Processor for Deep Neural Networks Acceleration.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2017
Comprehensive Evaluation of OpenCL-Based CNN Implementations for FPGAs.
Proceedings of the Advances in Computational Intelligence, 2017

End-to-end scalable FPGA accelerator for deep residual networks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A real-time 17-scale object detection accelerator with adaptive 2000-stage classification in 65nm CMOS.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Comprehensive Evaluation of OpenCL-based Convolutional Neural Network Accelerators in Xilinx and Altera FPGAs.
CoRR, 2016

High-performance face detection with CPU-FPGA acceleration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Energy-efficient reconstruction of compressively sensed bioelectrical signals with stochastic computing circuits.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015


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