Static-switching pulse domino: A switching-aware design technique for wide fan-in dynamic multiplexers. - Rahul Singh; Gi-Moon Hong; Mino Kim; Jihwan Park; Woo-Yeol Shin; Suhwan Kim 001 (Integr., 2012)

High-resolution and wide-dynamic range time-to-digital converter with a multi-phase cyclic Vernier delay line. - Mino Kim; Woo-Yeol Shin; Gi-Moon Hong; Jihwan Park; Joo-Hyung Chae; Nan Xing; Jong-Kwan Woo; Suhwan Kim 001 (ESSCIRC, 2013)

A 1.74mW/GHz 0.11-2.5GHz fast-locking, jitter-reducing, 180° phase-shift digital DLL with a window phase detector for LPDDR4 memory controllers. - Joo-Hyung Chae; Gi-Moon Hong; Jihwan Park; Mino Kim; Hyeongjun Ko; Woo-Yeol Shin; Hankyu Chi; Deog-Kyoon Jeong; Suhwan Kim 001 (A-SSCC, 2015)

Phase shift keying demodulator with decision feedback phase-locked loop. - Jae-Whan Lee; Mino Kim; Jihwan Park; Gi-Moon Hong; Suhwan Kim 001 (ISCAS, 2016)

A Sub-1.0-V On-Chip CMOS Thermometer With a Folded Temperature Sensor for Low-Power Mobile DRAM. - Hyunjoong Lee; Daeyong Shim; Cyuyeol Rhee; Mino Kim; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

A 0.13pJ/bit, referenceless transceiver with clock edge modulation for a wired intra-BAN communication. - Jihwan Park; Gi-Moon Hong; Mino Kim; Joo-Hyung Chae; Suhwan Kim 001 (ISLPED, 2017)

An 8Gb/s adaptive DFE with level calibration using training data pattern for mobile DRAM interface. - Minchang Kim; Jihwan Park; Joo-Hyung Chae; Hyeongjun Ko; Mino Kim; Suhwan Kim 001 (ISOCC, 2017)

A 3.2 Gb/s 16-Channel Transmitter for Intra-Panel Interfaces, With Independently Controllable Output Swing, Common-Mode Voltage, and Equalization. - Joo-Hyung Chae; Mino Kim; Gi-Moon Hong; Jihwan Park; Suhwan Kim 001 (IEEE Access, 2018)

A 4266 Mb/s/pin LPDDR4 Interface With An Asynchronous Feedback CTLE and An Adaptive 3-Step Eye Detection Algorithm for Memory Controller. - Mino Kim; Joo-Hyung Chae; Sungphil Choi; Gi-Moon Hong; Hyeongjun Ko; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 9Gb/s Wide Output Range Transmitter With 2D Binary-Segmented Driver and Dual-Loop Calibration for Intra-Panel Interfaces. - Yong-Un Jeong; Jihwan Park; Mino Kim; Joo-Hyung Chae; Jaekwang Yun; Hyunjoong Lee; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Controller PHY for Managed DRAM Solution With Damping-Resistor-Aided Pulse-Based Feed-Forward Equalizer. - Hyeongjun Ko; Mino Kim; Hyunkyu Park 002; Sangyoon Lee 006; Jaewook Kim; Suhwan Kim 001; Joo-Hyung Chae (IEEE J. Solid State Circuits, 2021)

13.8 A 1a-nm 1.05V 10.5Gb/s/pin 16Gb LPDDR5 Turbo DRAM with WCK Correction Strategy, a Voltage-Offset-Calibrated Receiver and Parasitic Capacitance Reduction. - Yangho Seo; Jihee Choi; Sunki Cho; Hyunwook Han; Wonjong Kim; Gyeongha Ryu; Jungil Ahn; Younga Cho; Sungphil Choi; Seohee Lee; Wooju Lee; Chaehyuk Lee; et al. (ISSCC, 2024)