An equalizing and channel coding processor for GSM terminals. - Minoru Okamoto; Toshihiro Ishikawa; S. Marui; Masayuki Yamasaki; Katsuhiko Ueda; Nobuo Asano; Mitsuru Uesugi; Yoshiko Saitoh; Yukihiro Fujimoto; Susumu Furushima (ICASSP, 1995)

An 80-MOPS-peak high-speed and low-power-consumption 16-b digital signal processor. - Hideyuki Kabuo; Minoru Okamoto; Isao Tanaka; Hiroyuki Yasoshima; Shinichi Marui; Masayuki Yamasaki; Toshio Sugimura; Katsuhiko Ueda; Toshihlro Ishikawa; Hidetoshi Suzuki; Ryuichi Asahi (IEEE J. Solid State Circuits, 1996)

160-Gbit/s Full Channel Optical Time-Division Demultiplexer Based on SOA-Array Integrated PLC and Its Application to OTDM Transmission Experiment. - Ippei Shake; Hidehiko Takara; Ikuo Ogawa; Tsutomu Kitoh; Minoru Okamoto; Katsuaki Magari; Takuya Ohara; Satoki Kawanishi (IEICE Trans. Commun., 2005)

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems. - Yasushi Amamiya; Shunichi Kaeriyama; Hidemi Noguchi; Zin Yamazaki; Tomoyuki Yamase; Ken'ichi Hosoya; Minoru Okamoto; Shiro Tomari; Hiroshi Yamaguchi; Hiroaki Shoda; Hironobu Ikeda; Shinji Tanaka; et al. (ISSCC, 2009)

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems. - Shunichi Kaeriyama; Yasushi Amamiya; Hidemi Noguchi; Zin Yamazaki; Tomoyuki Yamase; Ken'ichi Hosoya; Minoru Okamoto; Shiro Tomari; Hiroshi Yamaguchi; Hiroaki Shoda; Hironobu Ikeda; Shinji Tanaka; et al. (IEEE J. Solid State Circuits, 2009)