An optically differential reconfigurable gate array and its power consumption estimation. - Minoru Watanabe; Fuminori Kobayashi (FPT, 2002)

An Optically Differential Reconfigurable Gate Array with a Dynamic Reconfiguration Circuit. - Minoru Watanabe; Fuminori Kobayashi (IPDPS, 2003)

An FPGA Implementation of Finite Physical Quantity Neural Network. - Takashi Sotohebo; Minoru Watanabe; Funtinori Kobayashi (J. Robotics Mechatronics, 2003)

Testing Method for Optical Connections Using Gate Array Structure in ORGAs. - Minoru Watanabe; Fuminori Kobayashi (ERSA, 2004)

Timing Analysis of an Optically Differential Reconfigurable Gate Array for Dynamically Reconfigurable Processors. - Minoru Watanabe; Fuminori Kobayashi (ERSA, 2004)

A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. - Minoru Watanabe; Fuminori Kobayashi (FPL, 2004)

An optically differential reconfigurable gate array using a 0.18 μm CMOS process. - Minoru Watanabe; Fuminori Kobayashi (SoCC, 2004)

An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. - Minoru Watanabe; Fuminori Kobayashi (VLSI Design, 2004)

Rapid Reconfiguration of an Optically Differential Reconfigurable Gate Array with Pulse Lasers. - Mototsugu Miyano; Minoru Watanabe; Fuminori Kobayashi (FPT, 2005)

A Zero-Overhead Dynamic Optically Reconfigurable Gate Array. - Minoru Watanabe; Fuminori Kobayashi (FPT, 2005)

An Optically Differential Reconfigurable Gate Array VLSI Chip with a Dynamic Reconfiguration Circuit. - Minoru Watanabe; Fuminori Kobayashi (IPDPS, 2005)

A 16, 000-gate-count optically reconfigurable gate array in a standard 0.35µm CMOS technology. - Minoru Watanabe; Fuminori Kobayashi (ISCAS (2), 2005)

Optically Differential Reconfigurable Gate Array Using an Optical System with VCSELs. - Mototsugu Miyano; Minoru Watanabe; Fuminori Kobayashi (ISVLSI, 2005)

An Improved Dynamic Optically Reconfigurable Gate Array. - Minoru Watanabe; Fuminori Kobayashi (ISVLSI, 2005)

Optically Reconfigurable Gate Arrays vs. ASICs. - Minoru Watanabe; Fuminori Kobayashi (APCCAS, 2006)

A 1, 632 Gate-Count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. - Minoru Watanabe; Fuminori Kobayashi (ARC, 2006)

A 476-gate-count dynamic optically reconfigurable gate array VLSI chip in a standard 0.35 micrometer CMOS technology. - Minoru Watanabe; Fuminori Kobayashi (ASP-DAC, 2006)

Logic Synthesis and Place-and-Route Environment for ORGAs. - Minoru Watanabe; Fuminori Kobayashi (ERSA, 2006)

Shield Effect Analysis for a Gate Array on An Optically Reconfigurable Gate Array. - Minoru Watanabe; Fuminori Kobayashi (ERSA, 2006)

Differential Reconfiguration Architecture suitable for a Holographic Memory. - Minoru Watanabe; Mototsugu Miyano; Fuminori Kobayashi (ERSA, 2006)

A Reconfiguration Speed Adjustment Technique for ORGAs with a Holographic Memory. - Minoru Watanabe; Fuminori Kobayashi (FPL, 2006)

Power consumption advantage of a dynamic optically reconfigurable gate array. - Minoru Watanabe; Fuminori Kobayashi (IPDPS, 2006)

An optically differential reconfigurable gate array with a holographic memory. - Minoru Watanabe; Mototsugu Miyano; Fuminori Kobayashi (IPDPS, 2006)

A 0.35um CMOS 1, 632-gate-count Zero-Overhead Dynamic Optically Reconfigurable Gate Array VLSI. - Minoru Watanabe; Fuminori Kobayashi (ASP-DAC, 2007)

Optimization of Reconfiguration-speed Control Bits for an Optically Reconfigurable Gate Array. - Minoru Watanabe (ERSA, 2007)

272 Gate Count Optically Differential Reconfigurable Gate Array VLSI. - Minoru Watanabe; Takenori Shiki; Fuminori Kobayashi (ERSA, 2007)

A 62.5 ns holographic reconfiguration of an optically differential reconfigurable gate array. - Mao Nakajima; Minoru Watanabe (FPT, 2007)

Reconfiguration performance analysis of a dynamic optically reconfigurable gate array architecture. - Daisaku Seto; Minoru Watanabe (FPT, 2007)

A multi-context holographic memory recording system for Optically Reconfigurable Gate Arrays. - Rio Miyazaki; Minoru Watanabe; Fuminori Kobayashi (IPDPS, 2007)

Holographic memory reconfigurable VLSI. - Minoru Watanabe; Fuminori Kobayashi (ISCAS, 2007)

An 11, 424 gate-count zero-overhead dynamic optically reconfigurable gate array VLSI. - Minoru Watanabe (SoCC, 2007)

A Double or Triple Module Redundancy Model Exploiting Dynamic Reconfigurations. - Kouhi Shinohara; Minoru Watanabe (AHS, 2008)

Dynamic holographic reconfiguration on a four-context ODRGA. - Mao Nakajima; Minoru Watanabe (ASAP, 2008)

MISC: Mono Instruction-Set Computer based on Dynamic Reconfiguration - a 6502 Perspective. - Fuminori Kobayashi; Yasuyuki Morikawa; Minoru Watanabe (ERSA, 2008)

A 770ns Holographic Reconfiguration of a Four-Context DORGA. - Mao Nakajima; Minoru Watanabe (ERSA, 2008)

Inversion/non-inversion zero-overhead dynamic optically reconfigurable gate array VLSI. - Shinichi Kato; Minoru Watanabe (FPT, 2008)

An analog reconfiguration-period adjustment technique for optically reconfigurable gate arrays. - Takayuki Mabuchi; Minoru Watanabe (FPT, 2008)

An 11, 424-gate dynamic optically reconfigurable gate array VLSI. - Mao Nakajima; Minoru Watanabe (FPT, 2008)

A 937.5 ns multi-context holographic configuration with a 30.75 mus retention time. - Mao Nakajima; Daisaku Seto; Minoru Watanabe (IPDPS, 2008)

Defect tolerance of holographic configurations in ORGAs. - Kouhi Shinohara; Minoru Watanabe (IPDPS, 2008)

A Dynamic Optically Reconfigurable Gate Array with a Silver-Halide Holographic Memory. - Daisaku Seto; Minoru Watanabe (ISVLSI, 2008)

Analysis of retention time under multi-configuration on a DORGA. - Daisaku Seto; Minoru Watanabe (SoCC, 2008)

An Acceleration and Optimization Method for Optical Reconfiguration. - Minoru Watanabe; Naoki Yamaguchi (VLSI Design, 2008)

An Optical Reconfiguration System with Four Contexts. - Naoki Yamaguchi; Minoru Watanabe (VLSI Design, 2008)

Defect Tolerance of an Optically Reconfigurable Gate Array with a One-time Writable Volume Holographic Memory. - Takayuki Mabuchi; Kenji Miyashiro; Minoru Watanabe; Akifumi Ogiwara (AHS, 2009)

A Sixteen-Context Dynamic Optically Reconfigurable Gate Array. - Mao Nakajima; Minoru Watanabe (AHS, 2009)

Fast Optical Reconfiguration of a Nine-Context DORGA. - Mao Nakajima; Minoru Watanabe (ARC, 2009)

A 16-context Optically Reconfigurable Gate Array. - Mao Nakajima; Minoru Watanabe (ASAP, 2009)

An 11, 424 gate-count dynamic optically reconfigurable gate array with a photodiode memory architecture. - Daisaku Seto; Minoru Watanabe (ASP-DAC, 2009)

A Multi-Context Programmable Optically Reconfigurable Gate Array. - Shinya Kubota; Minoru Watanabe (ERSA, 2009)

Optically Reconfigurable Gate Array with a One-Time Writable Holographic Memory. - Takayuki Mabuchi; Kenji Miyashiro; Minoru Watanabe; Akifumi Ogiwara (ERSA, 2009)

Alignment compensation method for an optically reconfigurable gate array. - Hironobu Morita; Minoru Watanabe (ERSA, 2009)

Mems optically reconfigurable gate array. - Hironobu Morita; Minoru Watanabe (FPL, 2009)

A nine-context programmable optically reconfigurable gate array with semiconductor lasers. - Shinya Kubota; Minoru Watanabe (ACM Great Lakes Symposium on VLSI, 2009)

A 13.75 ns Holographic Reconfiguration of an Optically Differential Reconfigurable Gate Array. - Mao Nakajima; Minoru Watanabe (IIH-MSP, 2009)

Fast Reconfiguration Experiments of an Optically Differential Reconfigurable Gate Array with Nine Configuration Contexts. - Mao Nakajima; Minoru Watanabe (ISCAS, 2009)

Inversion/Non-inversion Implementation for an 11, 424 Gate-Count Dynamic Optically Reconfigurable Gate Array VLSI. - Shinichi Kato; Minoru Watanabe (SAMOS, 2009)

Binary MEMS Optically Reconfigurable Gate Array. - Hironobu Morita; Minoru Watanabe (ACIS-ICIS, 2010)

Acceleration method of optical reconfigurations using analog configuration contexts. - Yuji Aoyama; Minoru Watanabe (AHS, 2010)

Recovery method for a turn-off failure mode of a laser array on an ORGA. - Daisaku Seto; Minoru Watanabe (AHS, 2010)

MEMS Dynamic Optically Reconfigurable Gate Array Usable under a Space Radiation Environment. - Daisaku Seto; Minoru Watanabe (ARC, 2010)

Recovery Method for a Laser Array Failure on Dynamic Optically Reconfigurable Gate Arrays. - Daisaku Seto; Minoru Watanabe (DFT, 2010)

Partial Block-by-Block Reconfiguration for a Dynamic Optically Reconfigurable Gate Array. - Daisaku Seto; Minoru Watanabe (ERSA, 2010)

Dynamically Reconfigurable Vision-Chip Architecture. - Maki Yasuda; Minoru Watanabe (FPL, 2010)

Othello Solver based on a soft-core MIMD processor array. - Takayuki Mabuchi; Takahiro Watanabe; Retsu Moriwaki; Yuji Aoyama; Amarjargal Gundjalam; Yuichiro Yamaji; Hironari Nakada; Minoru Watanabe (FPT, 2010)

A 64-context MEMS optically reconfigurable gate array. - Yuichiro Yamaji; Minoru Watanabe (FPT, 2010)

A 100-context optically reconfigurable gate array. - Mao Nakajima; Minoru Watanabe (ISCAS, 2010)

Estimation of characteristic variation of photodiodes and its compensation method in an optically reconfigurable gate array. - Yuji Aoyama; Minoru Watanabe (SoCC, 2010)

Optically reconflgurable gate array with a polymer-dispersed liquid crystal holographic memory. - Takayuki Mabuchi; Minoru Watanabe; Akifumi Ogiwara; Fuminori Kobayashi (AHS, 2011)

MEMS Interleaving Read Operation of a Holographic Memory for Optically Reconfigurable Gate Arrays. - Hironobu Morita; Minoru Watanabe (ARC, 2011)

Dependable Optically Reconfigurable Gate Array with a Phase-Modulation Type Holographic Memory. - Takahiro Watanabe; Minoru Watanabe (FPL, 2011)

An FPGA Connect6 Solver with a two-stage pipelined evaluation. - Takahiro Watanabe; Retsu Moriwaki; Yuichiro Yamaji; Yuki Kamikubo; Yuki Torigai; Yuki Nihira; Takashi Yoza; Yumiko Ueno; Yuji Aoyama; Minoru Watanabe (FPT, 2011)

Triple module redundancy scheme on an optically reconfigure gate array. - Yuki Torigai; Minoru Watanabe (ISOCC, 2011)

A 144-configuration context MEMS optically reconfigurable gate array. - Yuichiro Yamaji; Minoru Watanabe (SoCC, 2011)

A MEMS writer system embedded for a programmable optically reconfigurable gate array. - Shinya Kubota; Minoru Watanabe (SIGARCH Comput. Archit. News, 2011)

Fast Optical Reconfiguration of a Nine-Context DORGA Using a Speed Adjustment Control. - Mao Nakajima; Minoru Watanabe (ACM Trans. Reconfigurable Technol. Syst., 2011)

A 16-configuration-context dynamic optically reconfigurable gate array with a dependable laser array. - Takashi Yoza; Minoru Watanabe (AHS, 2012)

Triple Module Redundancy of a Laser Array Driver Circuit for Optically Reconfigurable Gate Arrays. - Takahiro Watanabe; Minoru Watanabe (ARC, 2012)

A 16-configuration-context robust optically reconfigurable gate array with a reconfiguration speed adjustment function. - Takashi Yoza; Minoru Watanabe (FPL, 2012)

High Speed - Low Power Optical Configuration on an ORGA with a Phase-modulation Type Holographic Memory. - Takahiro Watanabe; Minoru Watanabe (IPDPS Workshops, 2012)

0.18-um CMOS Process Highly Sensitive Differential Optically Reconfigurable Gate Array VLSI. - Takahiro Watanabe; Minoru Watanabe (ISVLSI, 2012)

Inversion/non-inversion reconfiguration scheme for a 0.18 J.1m CMOS process optically reconfigurable gate array VLSI. - Takahiro Watanabe; Minoru Watanabe (MWSCAS, 2012)

A Uniform Partitioning Method for Mono-Instruction Set Computer (MISC). - Hiroyuki Ito; Minoru Watanabe (NBiS, 2012)

Gray-level image recognition on a dynamically reconfigurable vision architecture. - Yuki Kamikubo; Minoru Watanabe; Shoji Kawahito (SoCC, 2012)

0.18 μm CMOS proess high-sensitivity optially reonfgurable gatearray VLSI. - Takahiro Watanabe; Minoru Watanabe (SIGARCH Comput. Archit. News, 2012)

Four-configuration-context optically reconfigurable gate array with a MEMS interleaving method. - Yuichiro Yamaji; Minoru Watanabe (AHS, 2013)

Dependability-Increasing Method of Processors under a Space Radiation Environment. - Yuya Shirahashi; Minoru Watanabe (ARC, 2013)

Image recognition operation on a dynamically reconfigurable vison architecture. - Yuki Kamikubo; Minoru Watanabe; Shoji Kawahito (FPL, 2013)

Color configuration method for an optically reconfigurable gate array. - Takumi Fujimori; Minoru Watanabe (FPT, 2013)

FPGA Blokus Duo Solver using a massively parallel architecture. - Takashi Yoza; Retsu Moriwaki; Yuki Torigai; Yuki Kamikubo; Takayuki Kubota; Takahiro Watanabe; Takumi Fujimori; Hiroyuki Ito; Masato Seo; Kouta Akagi; Yuichiro Yamaji; Minoru Watanabe (FPT, 2013)

0.18 μm CMOS process photodiode memory. - Takayuki Kubota; Minoru Watanabe (ISCAS, 2013)

Dependability-increasing technique for a multi-context optically reconfigurable gate array. - Akira Tanigawa; Minoru Watanabe (ISCAS, 2013)

Fourier transformation on an optically reconfigurable gate array. - Hiroyuki Ito; Minoru Watanabe (MWSCAS, 2013)

Enhanced Radiation Tolerance of an Optically Reconfigurable Gate Array by Exploiting an Inversion/Non-inversion Implementation. - Takashi Yoza; Minoru Watanabe (ARC, 2014)

Optically reconfigurable gate array with an angle-multiplexed holographic memory. - Retsu Moriwaki; Hikaru Maekawa; Akifumi Ogiwara; Minoru Watanabe (ACM Great Lakes Symposium on VLSI, 2014)

Radiation Tolerance of Color Configuration on an Optically Reconfigurable Gate Array. - Takumi Fujimori; Minoru Watanabe (IPDPS Workshops, 2014)

Image recognition system using an optical Fourier transform on a dynamically reconfigurable vision architecture. - Yuki Kamikubo; Minoru Watanabe; Shoji Kawahito (ISCAS, 2014)

Holographic scrubbing technique for a programmable gate array. - Minoru Watanabe; Takumi Fujimori (AHS, 2015)

Total Ionizing Dose Effects of Optical Components on an Optically Reconfigurable Gate Array. - Retsu Moriwaki; Hiroyuki Ito; Kouta Akagi; Minoru Watanabe; Akifumi Ogiwara (ARC, 2015)

Parallel-Operation-Oriented Optically Reconfigurable Gate Array. - Takumi Fujimori; Minoru Watanabe (ARCS, 2015)

FPGA Trax Solver based on a neural network design. - Takumi Fujimori; Tomoya Akabe; Yoshizumi Ito; Kouta Akagi; Shinya Furukawa; Hiroki Shinba; Aoi Tanibata; Minoru Watanabe (FPT, 2015)

Sustainable advantage of a parallel configuration in an optical FPGA. - Minoru Watanabe (SII, 2015)

Direct optical communication on an optically reconfigurable gate array. - Shinya Furukawa; Ili Shairah Abdul Halim; Minoru Watanabe; Fuminori Kobayashi (FGCT, 2016)

A 200 Mrad Radiation Tolerance of a Polymer-Dispersed Liquid Crystal Holographic Memory. - Yoshizumi Ito; Minoru Watanabe; Akifumi Ogiwara (HPCC/SmartCity/DSS, 2016)

Full FPGA game machine. - Takumi Fujimori; Minoru Watanabe (ICCE, 2016)

Photodiode sensitivity measurement methodology using low light intensity for optically reconfigurable gate arrays. - Bharat Ramanathan; Minoru Watanabe (ICCSE, 2016)

Reconfiguration Performance Recovery on Optically Reconfigurable Gate Arrays. - Tomoya Akabe; Minoru Watanabe (VLSID, 2016)

500 Mrad total-ionizing-dose tolerance of a holographic memory on an optical FPGA. - Yoshizumi Ito; Minoru Watanabe; Akifumi Ogiwara (AHS, 2017)

Optically reconfigurable gate array platform for mono-instruction set computer architecture. - Hiroki Shinba; Minoru Watanabe (CCWC, 2017)

Holographic Memory Calculation FPGA Accelerator for Optically Reconfigurable Gate Arrays. - Takumi Fujimori; Minoru Watanabe (DASC/PiCom/DataCom/CyberSciTech, 2017)

Multi-context scrubbing method. - Takumi Fujimori; Minoru Watanabe (MWSCAS, 2017)

Radiation tolerance demonstration of high-speed scrubbing on an optically reconfigurable gate array. - Takumi Fujimori; Minoru Watanabe (SoCC, 2017)

Advanced Devices and Architectures. - Masato Motomura; Masanori Hariyama; Minoru Watanabe (Principles and Structures of FPGAs, 2018)

A 400 Mrad radiation-hardened optoelectronic embedded system with a silver-halide holographic memory. - Takumi Fujimori; Minoru Watanabe (AHS, 2018)

High total-ionizing-dose tolerance field programmable gate array. - Takumi Fujimori; Minoru Watanabe (ISCAS, 2018)

Foreword. - Minoru Watanabe (IEICE Trans. Inf. Syst., 2018)

Full-hardware triple modular and penta-modular redundancies using a high frequency majority voting operation. - Masaki Watanabe; Minoru Watanabe (APCCAS, 2019)

FPGA implementation of a robot control algorithm. - Yusuke Takaki; Kohei Nagasu; Shin Abiko; Minoru Watanabe; Kentaro Sano (ETFA, 2019)

Radiation-degradation Analysis and a Circuit Performance Improvement Method for Optoelectronic Field Programmable Gate Array. - Hirotoshi Ito; Minoru Watanabe (SoCC, 2019)

Total-ionizing-dose tolerance evaluation of an optoelectronic field programmable gate array VLSI during operation. - Hirotoshi Ito; Minoru Watanabe (FPT, 2021)

Sequential Circuit Implementation Method for Multi-Context Scrubbing Operations on FPGAs. - Kurea Murakami; Minoru Watanabe (ISCAS, 2021)

Optically Reconfigurable Gate Array VLSI That Can Support a Perfect Parallel Configuration. - Sae Goto; Minoru Watanabe; Nobuya Watanabe (APCCAS, 2022)

Convolutional neural network implementations using Vitis AI. - Akihiko Ushiroyama; Minoru Watanabe; Nobuya Watanabe; Akira Nagoya (CCWC, 2022)

Total Dose Tolerance Analysis of an Optically Reconfigurable Gate Array VLSI. - Kaho Yamada; Takeshi Okazaki; Minoru Watanabe; Nobuya Watanabe (ICECS 2022, 2022)

Total-Ionizing-Dose Tolerance Analysis of a Radiation-Hardened Image Sensor. - Daisuke Bamba; Minoru Watanabe; Nobuya Watanabe (ICCE, 2023)

Radiation-hardened stabilized power supply unit based on bipolar transistors. - Takato Tanizawa; Minoru Watanabe (ICM, 2023)

Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock. - Minoru Watanabe (ISCAS, 2023)

Multi-context-scrubbing operation for a 1-bit counter circuit. - Kakeru Ando; Minoru Watanabe; Nobuya Watanabe (NEWCAS, 2023)

An optically reconfigurable gate array VLSI driven by an unstabilized power supply unit. - Masashi Tsujino; Minoru Watanabe; Nobuya Watanabe (SOCC, 2023)

Analysis of Clock Tree Buffer Degradation Caused by Radiation. - Minoru Watanabe (ARC, 2024)

Voltage Range Evaluation of An Optically Reconfigurable Gate Array VLSI. - Yuki Shimamura; Minoru Watanabe; Nobuya Watanabe (ASAP, 2024)

Parallel configuration experiment for a radiation-hardened optically reconfigurable gate array with a holographic polymer-dispersed liquid crystal memory. - Sae Goto; Minoru Watanabe; Akifumi Ogiwara; Nobuya Watanabe (ICCE, 2024)

Holographic memory formed by different laser wavelengths in laser combiner system for optically reconfigurable gate array. - Akifumi Ogiwara; Minoru Watanabe (ICCE, 2024)

Remote monitoring system for optically reconfigurable gate arrays in radiation environments. - Utsuki Sekioka; Minoru Watanabe; Nobuya Watanabe (ICCE, 2024)

Wafer-scale VLSI realization using programmable architecture. - Atsushi Takata; Minoru Watanabe; Nobuya Watanabe (ICCE, 2024)

Application design system for high-speed dynamically reconfigurable gate arrays. - Nobuya Watanabe; Ryoya Ishitani; Minoru Watanabe (ICCE, 2024)

Fast-neutron soft-error tolerance experimentation with a radiation-hardened optically reconfigurable gate array. - Minoru Watanabe; Makoto Inami Kobayashi; Mitsutaka Isobe; Kunihiro Ogawa; Shigeo Matsuyama; Misako Miwa (ICCE, 2024)

Ring oscillator based clock generation for a radiation-hardened optically reconfigurable gate array VLSI. - Shintaro Takatsuki; Minoru Watanabe; Nobuya Watanabe (SOCC, 2024)

Implementation of Mono Instruction Set Computer with Small Register Files. - Soma Imai; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Development of a Radiation-Hardened JTAG Interface for Optically Reconfigurable Gate Arrays. - Naoki Nagamine; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Demonstration of a Clock Distribution Method using Switching Matrices and a Two-Phase Clock Signal on an FPGA. - Ayumu Ogura; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Radiation Degradation Evaluation of the Dynamic Configuration Circuit on An Optically Reconfigurable Gate Array VLSI. - Seiji Ohashi; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Radiation-Hardened Triple Modular Redundant Serial Communication System Using Triple Communication Lines. - Utsuki Sekioka; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Realization of Wafer-Scale VLSI Using Optical Configuration Architecture. - Atsushi Takata; Minoru Watanabe; Nobuya Watanabe (ICCE, 2025)

Fast-Neutron Soft-Error Tolerance of a Radiation-Hardened Repairable Field Programmable Gate Array. - Minoru Watanabe; Makoto Kobayashi; Mitsutaka Isobe; Kunihiro Ogawa; Shingo Tamaki; Isao Murata; Sachie Kusaka (ICCE, 2025)

Triple Modular Redundancy Logic Design from High-Level Hardware Description. - Nobuya Watanabe; Minoru Watanabe (ICCE, 2025)