Reconfigurable Cipher Processing Framework and Implementation. - Jingfei Jiang; Xiaoqiang Ni; Minxuan Zhang (APPT, 2003)

Dual-Stack Return Address Predictor. - Caixia Sun; Minxuan Zhang (ICESS, 2004)

A Fetch Policy Maximizing Throughput and Fairness for Two-Context SMT Processors. - Caixia Sun; Hong-Wei Tang; Minxuan Zhang (APPT, 2005)

Detecting Memory Access Errors with Flow-Sensitive Conditional Range Analysis. - Yimin Xia; Jun Luo; Minxuan Zhang (ICESS, 2005)

Enhancing DCache Warn Fetch Policy for SMT Processors. - Minxuan Zhang; Caixia Sun (ISPA, 2005)

Enhancing ICOUNT2.8 Fetch Policy with Better Fairness for SMT Processors. - Caixia Sun; Hong-Wei Tang; Minxuan Zhang (Asia-Pacific Computer Systems Architecture Conference, 2006)

An Architectural Leakage Power Reduction Method for Instruction Cache in Ultra Deep Submicron Microprocessors. - Chengyi Zhang; Hongwei Zhou; Minxuan Zhang; Zuocheng Xing (Asia-Pacific Computer Systems Architecture Conference, 2006)

Controlling Performance of a Time-Criticial Thread in SMT Processors by Instruction Fetch Policy. - Caixia Sun; Hong-Wei Tang; Minxuan Zhang (PDCAT, 2006)

Look-Ahead Adaptive Routing on k -Ary n -Trees. - Quanbao Sun; Liquan Xiao; Minxuan Zhang (APPT, 2007)

A Unified Compressed Cache Hierarchy With Partial Cache Line Prefetching Used for SMT Processor. - Tian Xinhua; Minxuan Zhang (CDES, 2007)

A Parallel Infrastructure on Dynamic EPIC SMT. - Qingying Deng; Minxuan Zhang; Jiang Jiang (ICA3PP, 2007)

A Unified Compressed Cache Hierarchy Using Simple Frequent Pattern Compression and Partial Cache Line Prefetching. - Xinhua Tian; Minxuan Zhang (ICESS, 2007)

Hardware-Based Multicast with Global Load Balance on k-ary n-trees. - Quanbao Sun; Minxuan Zhang; Liquan Xiao (ICPP, 2007)

Register File Management and Compiler Optimization on EDSMT. - Qingying Deng; Minxuan Zhang; Jiang Jiang (ISPA Workshops, 2007)

A Parallel Infrastructure on Dynamic EPIC SMT and Its Speculation Optimization. - Qingying Deng; Minxuan Zhang; Jiang Jiang (ISPA, 2007)

Dimensional Bubble Flow Control and Fully Adaptive Routing in the 2-D Mesh Network on Chip. - Canwen Xiao; Minxuan Zhang; Yong Dou; Zhitong Zhao (EUC (1), 2008)

A Global Replacement Based on Actual Set Association. - Peixiang Yan; Xianju Yang; Minxuan Zhang (ICESS, 2009)

Phase Characterization and Classification for Micro-architecture Soft Error. - Yu Cheng; Anguo Ma; Yuxing Tang; Minxuan Zhang (EUC, 2010)

Low Power Design for a Multi-core Multi-thread Microprocessor. - Yongwen Wang; Qianbing Zheng; Qiang Dou; Minxuan Zhang (GreenCom/CPSCom, 2010)

Towards Online Application Cache Behaviors Identification in CMPs. - Xiaomin Jia; Jiang Jiang; Tianlei Zhao; Shubo Qi; Minxuan Zhang (HPCC, 2010)

A high performance router with dynamic buffer allocation for on-chip interconnect networks. - Shubo Qi; Minxuan Zhang; Jinwen Li; Tianlei Zhao; Chengyi Zhang; Shaoqing Li (ICCD, 2010)

Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material. - Zhou Hailiang; Minxuan Zhang; Fang Liang; Hao Yue (ISVLSI, 2010)

A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network. - Shubo Qi; Jinwen Li; Zuocheng Xing; Xiaomin Jia; Minxuan Zhang (ISVLSI, 2010)

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip. - Chaochao Feng; Zhonghai Lu; Axel Jantsch; Jinwen Li; Minxuan Zhang (NoCArc@MICRO, 2010)

FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip. - Chaochao Feng; Zhonghai Lu; Axel Jantsch; Jinwen Li; Minxuan Zhang (SoCC, 2010)

Opitimization of tunneling carbon nanotube-FETs based on stair-case doping strategy. - Hailiang Zhou; Jiang Jiang; Minxuan Zhang; Liang Fang (Sci. China Inf. Sci., 2010)

Dynamic Program Behavior Identification for High Performance CMPs with Private LLCs. - Xiaomin Jia; Pingjing Lu; Caixia Sun; Minxuan Zhang (IEICE Trans. Inf. Syst., 2010)

Evaluation of deflection routing on various NoC topologies. - Chaochao Feng; Jinwen Li; Zhonghai Lu; Axel Jantsch; Minxuan Zhang (ASICON, 2011)

Timing-Driven Routing of High Fanout Nets. - Xun Chen; Jianwen Zhu; Minxuan Zhang (FPL, 2011)

Software/Hardware Framework for Generating Parallel Long-Period Random Numbers Using the WELL Method. - Yuan Li; Paul Chow; Jiang Jiang; Minxuan Zhang (FPL, 2011)

Accelerating the Extraction of Representative Behaviors of Programs with Dynamic Binary Translation. - Tianlei Zhao; Jiang Jiang; Guitao Fu; Shubo Qi; Xiaomin Jia; Minxuan Zhang (HPCC, 2011)

Characterizing Time-Varying Behavior and Predictability of Cache AVF. - Yu Cheng; Yongwen Wang; Zuocheng Xing; Minxuan Zhang (INCoS, 2011)

A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip. - Chaochao Feng; Minxuan Zhang; Jinwen Li; Jiang Jiang; Zhonghai Lu; Axel Jantsch (ISVLSI, 2011)

BP-NUCA: Cache Pressure-Aware Migration for High-Performance Caching in CMPs. - Xiaomin Jia; Jiang Jiang; Yongwen Wang; Shubo Qi; Tianlei Zhao; Guitao Fu; Minxuan Zhang (Comput. Informatics, 2011)

An Efficient Hardware Random Number Generator Based on the MT Method. - Yuan Li; Jiang Jiang; Hanqiang Cheng; Minxuan Zhang; Shaojun Wei (CIT, 2012)

Software/hardware framework for generating parallel Gaussian random numbers based on the Monty Python method. - Yuan Li; Paul Chow; Jiang Jiang; Minxuan Zhang; Shaojun Wei (FPT, 2012)

Adaptive Bubble Scheme with Minimal Buffers in Torus Networks. - Yongqing Wang; Minxuan Zhang; Qingchao Yu; Zhengbin Pang (HPCC-ICESS, 2012)

PSA-NUCA: A Pressure Self-Adapting Dynamic Non-uniform Cache Architecture. - Anwen Huang; Jun Gao; Wei Guo; Wenqiang Shi; Minxuan Zhang; Jiang Jiang (NAS, 2012)

A single-cycle output buffered router with layered switching for Networks-on-Chips. - Yancang Chen; Zhonghai Lu; Lunguo Xie; Jinwen Li; Minxuan Zhang (Comput. Electr. Eng., 2012)

Accurate and Simplified Prediction of L2 Cache Vulnerability for Cost-Efficient Soft Error Protection. - Yu Cheng; Anguo Ma; Minxuan Zhang (IEICE Trans. Inf. Syst., 2012)

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip. - Chaochao Feng; Zhonghai Lu; Axel Jantsch; Minxuan Zhang (IEICE Trans. Inf. Syst., 2012)

Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip. - Chaochao Feng; Zhonghai Lu; Axel Jantsch; Minxuan Zhang; Xianju Yang (IEICE Trans. Inf. Syst., 2012)

Adaptive Capacity Sharing through Probabilistic Controlled Placement. - Xianju Yang; Peixiang Yan; Jiang Jiang; Minxuan Zhang (J. Comput., 2012)

An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors. - Anwen Huang; Chao Song; Wei Guo; Peng Li; Minxuan Zhang (ASICON, 2013)

Wormhole Bubble in Torus Networks. - Yongqing Wang; Minxuan Zhang (NCCET, 2013)

Architecture and Implementation of a Reduced EPIC Processor. - Jun Gao; Minxuan Zhang; Zuocheng Xing; Chaochao Feng (IEICE Trans. Inf. Syst., 2013)

Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router. - Chaochao Feng; Zhonghai Lu; Axel Jantsch; Minxuan Zhang; Zuocheng Xing (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Assimilating Cleaning Operations with Flash-Level Parallelism for NAND Flash-Based Devices. - Ronghui Wang; Zhiguang Chen 001; Nong Xiao 001; Minxuan Zhang; Weihua Dong (CIT, 2014)

Effect of charge sharing on SEU sensitive area of 40-nm 6T SRAM cells. - Peng Li; Minxuan Zhang; Weicheng Zhang; Zhenyu Zhao; Chao Song; Hua Fan (IEICE Electron. Express, 2014)

Software/Hardware Parallel Long-Period Random Number Generation Framework Based on the WELL Method. - Yuan Li; Paul Chow; Jiang Jiang; Minxuan Zhang; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Improved access pattern for ROB soft error rate mitigation based on 3D integration technology. - Chao Song; Minxuan Zhang (3DIC, 2015)

Mitigation Techniques Against TSV-to-TSV Coupling in 3DIC. - Quan Deng; Minxuan Zhang; Zhenyu Zhao; Peng Li (NCCET, 2015)

Thermal-Aware Floorplanner for Multi-core 3D ICs with Interlayer Cooling. - Wei Guo; Minxuan Zhang; Peng Li; Chaoyun Yao; Hongwei Zhou (NCCET, 2015)

Impact of Heavy Ion Species and Energy on SEE Characteristics of Three-Dimensional Integrated Circuit. - Peng Li; Wei Guo; Zhenyu Zhao; Minxuan Zhang (NCCET, 2015)

Mitigating Soft Error Rate Through Selective Replication in Hybrid Architecture. - Chao Song; Minxuan Zhang (NCCET, 2015)

Partitioning Methods for Multicast in Bufferless 3D Network on Chip. - Chaoyun Yao; Chaochao Feng; Minxuan Zhang; Wei Guo; Shouzhong Zhu; Shaojun Wei (NCCET, 2015)

Towards high-performance packet processing on commodity multi-cores: current issues and future directions. - Lu Tang; Jinli Yan; Zhigang Sun; Tao Li 008; Minxuan Zhang (Sci. China Inf. Sci., 2015)

Floorplanner for multi-core micro-processors in 3D ICs with interlayer cooling system. - Wei Guo; Minxuan Zhang; Peng Li; Chaoyun Yao (IEICE Electron. Express, 2015)

SEU hardened layout design for SRAM cells based on SEU reversal. - Peng Li; Wei Guo; Zhenyu Zhao; Minxuan Zhang; Quan Deng (IEICE Electron. Express, 2015)

Exploring partitioning methods for multicast in 3D bufferless Network on Chip. - Chaoyun Yao; Chaochao Feng; Minxuan Zhang; Wei Guo; Shouzhong Zhu; Shaojun Wei (IEICE Electron. Express, 2015)

A Novel Hybrid Last Level Cache Based on Multi-retention STT-RAM Cells. - Hongguang Zhang; Minxuan Zhang; Zhenyu Zhao; Shuo Tian (ACA, 2016)

Hardware design of ML algorithm in MIMO-OFDM system. - Suncheng Xiang; Minxuan Zhang; Zuocheng Xing; Cang Liu (ICSAI, 2016)

Accelerating Nyström Kernel Independent Component Analysis with Many Integrated Core Architecture. - Lei Shan; He Wang; Weixia Xu; Canqun Yang; Minxuan Zhang (NCCET, 2016)

A Dynamic Multi-precision Fixed-Point Data Quantization Strategy for Convolutional Neural Network. - Lei Shan; Minxuan Zhang; Lin Deng; Guohui Gong (NCCET, 2016)

A New DVFS Algorithm Design for Multi-core Processor Chip. - Chengyi Zhang; Jiming Wang; Minxuan Zhang; Xiangdi Wu (NCCET, 2016)

A Novel L1 Cache Based on Volatile STT-RAM. - Hongguang Zhang; Minxuan Zhang (NCCET, 2016)

Sub-threshold Performance Driven Choice in Tunneling CNFETs. - Hailiang Zhou; Xiantuo Tang; Minxuan Zhang; Yue Hao (NCCET, 2016)

Thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system. - Wei Guo; Minxuan Zhang; Chaoyun Yao; Peng Li; Chaochao Feng; Hongwei Zhou (IEICE Electron. Express, 2016)

Towards warp-scheduler friendly STT-RAM/SRAM hybrid GPGPU register file design. - Quan Deng; Youtao Zhang; Minxuan Zhang; Jun Yang 002 (ICCAD, 2017)

Heterogeneous acceleration for CNN training with many integrated core. - Lei Shan; Canqun Yang; Weixia Xu; Minxuan Zhang (ICSPCC, 2017)

Delay Compensated Asynchronous Adam Algorithm for Deep Neural Networks. - Naiyang Guan; Lei Shan; Canqun Yang; Weixia Xu; Minxuan Zhang (ISPA/IUCC, 2017)

DrAcc: a DRAM based accelerator for accurate CNN inference. - Quan Deng; Lei Jiang 001; Youtao Zhang; Minxuan Zhang; Jun Yang 002 (DAC, 2018)

LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN Accelerator. - Quan Deng; Youtao Zhang; Minxuan Zhang; Jun Yang 002 (DAC, 2019)

FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. - Quan Deng; Youtao Zhang; Zhenyu Zhao; Shuzheng Zhang; Minxuan Zhang; Jun Yang 002 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)