A Generalization of Perfect Lee Codes over Gaussian Integers. - Carmen Martínez; Miquel Moretó; Ramón Beivide; Ernst M. Gabidulin (ISIT, 2006)

Dense Gaussian Networks: Suitable Topologies for On-Chip Multiprocessors. - Carmen Martínez; Enrique Vallejo 001; Ramón Beivide; Cruz Izu; Miquel Moretó (Int. J. Parallel Program., 2006)

Mixed-radix Twisted Torus Interconnection Networks. - José M. Cámara; Miquel Moretó; Enrique Vallejo 001; Ramón Beivide; José Miguel-Alonso; Carmen Martínez; Javier Navaridas (IPDPS, 2007)

Online Prediction of Applications Cache Utility. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (ICSAMOS, 2007)

Explaining Dynamic Cache Partitioning Speed Ups. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (IEEE Comput. Archit. Lett., 2007)

Evolutionary system for prediction and optimization of hardware architecture performance. - Pedro Ángel Castillo Valdivieso; Juan Julián Merelo Guervós; Miquel Moretó; Francisco J. Cazorla; Mateo Valero; Antonio Miguel Mora; Juan Luis Jiménez Laredo; Sally A. McKee (IEEE Congress on Evolutionary Computation, 2008)

Architecture Performance Prediction Using Evolutionary Artificial Neural Networks. - Pedro A. Castillo; Antonio Miguel Mora; Juan Julián Merelo Guervós; Juan Luis Jiménez Laredo; Miquel Moretó; Francisco J. Cazorla; Mateo Valero; Sally A. McKee (EvoWorkshops, 2008)

MLP-Aware Dynamic Cache Partitioning. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (HiPEAC, 2008)

Multicore Resource Management. - Kyle J. Nesbit; Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero; James E. Smith 001 (IEEE Micro, 2008)

Modeling Toroidal Networks with the Gaussian Integers. - Carmen Martínez; Ramón Beivide; Esteban Stafford; Miquel Moretó; Ernst M. Gabidulin (IEEE Trans. Computers, 2008)

ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs. - Carlos Luque; Miquel Moretó; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Mateo Valero (PACT, 2009)

CPU Accounting in CMP Processors. - Carlos Luque; Miquel Moretó; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Mateo Valero (IEEE Comput. Archit. Lett., 2009)

FlexDCP: a QoS framework for CMP architectures. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Rizos Sakellariou; Mateo Valero (ACM SIGOPS Oper. Syst. Rev., 2009)

Load balancing using dynamic cache allocation. - Miquel Moretó; Francisco J. Cazorla; Rizos Sakellariou; Mateo Valero (Conf. Computing Frontiers, 2010)

Adapting cache partitioning algorithms to pseudo-LRU replacement policies. - Kamil Kedzierski; Miquel Moretó; Francisco J. Cazorla; Mateo Valero (IPDPS, 2010)

Twisted Torus Topologies for Enhanced Interconnection Networks. - José M. Cámara; Miquel Moretó; Enrique Vallejo 001; Ramón Beivide; José Miguel-Alonso; Carmen Martínez; Javier Navaridas (IEEE Trans. Parallel Distributed Syst., 2010)

Improving cache Behavior in CMP architectures throug cache partitioning techniques. - Miquel Moretó (2010)

Simulating Whole Supercomputer Applications. - Juan Gonzalez; Judit Giménez; Marc Casas; Miquel Moretó; Alex Ramírez; Jesús Labarta; Mateo Valero (IEEE Micro, 2011)

Dynamic Cache Partitioning Based on the MLP of Cache Misses. - Miquel Moretó; Francisco J. Cazorla; Alex Ramírez; Mateo Valero (Trans. High Perform. Embed. Archit. Compil., 2011)

Optimal task assignment in multithreaded processors: a statistical approach. - Petar Radojkovic; Vladimir Cakarevic; Miquel Moretó; Javier Verdú; Alex Pajuelo; Francisco J. Cazorla; Mario Nemirovsky; Mateo Valero (ASPLOS, 2012)

Characterizing thread placement in the IBM POWER7 processor. - Stelios Manousopoulos; Miquel Moretó; Roberto Gioiosa; Nectarios Koziris; Francisco J. Cazorla (IISWC, 2012)

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem. - Petar Radojkovic; Paul M. Carpenter; Miquel Moretó; Alex Ramírez; Francisco J. Cazorla (MICRO, 2012)

CPU Accounting for Multicore Processors. - Carlos Luque; Miquel Moretó; Francisco J. Cazorla; Roberto Gioiosa; Alper Buyuktosunoglu; Mateo Valero (IEEE Trans. Computers, 2012)

Tessellation: refactoring the OS around explicit resource containers with continuous adaptation. - Juan A. Colmenares; Gage Eads; Steven A. Hofmeyr; Sarah Bird; Miquel Moretó; David Chou; Brian Gluzman; Eric Roman; Davide B. Bartolini; Nitesh Mor; Krste Asanovic; John Kubiatowicz (DAC, 2013)

On the convergence of mainstream and mission-critical markets. - Sylvain Girbal; Miquel Moretó; Arnaud Grasset; Jaume Abella 001; Eduardo Quiñones; Francisco J. Cazorla; Sami Yehia (DAC, 2013)

A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness. - Henry Cook; Miquel Moretó; Sarah Bird; Khanh Dao; David A. Patterson 001; Krste Asanovic (ISCA, 2013)

Task mapping in rectangular twisted tori. - Cristobal Camarero; Enrique Vallejo 001; Carmen Martínez; Miquel Moretó; Ramón Beivide (SpringSim (HPC), 2013)

Hardware support for accurate per-task energy metering in multicore systems. - Qixiao Liu; Miquel Moretó; Víctor Jiménez; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (ACM Trans. Archit. Code Optim., 2013)

Fair CPU time accounting in CMP+SMT processors. - Carlos Luque; Miquel Moretó; Francisco J. Cazorla; Mateo Valero (ACM Trans. Archit. Code Optim., 2013)

Evaluating Execution Time Predictability of Task-Based Programs on Multi-Core Processors. - Thomas Grass; Alejandro Rico; Marc Casas; Miquel Moretó; Alex Ramírez (Euro-Par Workshops (2), 2014)

DReAM: Per-Task DRAM Energy Metering in Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (Euro-Par, 2014)

Per-task Energy Accounting in Computing Systems. - Qixiao Liu; Víctor Jiménez; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (IEEE Comput. Archit. Lett., 2014)

Runtime-Aware Architectures: A First Approach. - Mateo Valero; Miquel Moretó; Marc Casas; Eduard Ayguadé; Jesús Labarta (Supercomput. Front. Innov., 2014)

Runtime-Guided Management of Scratchpad Memories in Multicore Architectures. - Lluc Alvarez; Miquel Moretó; Marc Casas; Emilio Castillo; Xavier Martorell; Jesús Labarta; Eduard Ayguadé; Mateo Valero (PACT, 2015)

Runtime-Aware Architectures. - Marc Casas; Miquel Moretó; Lluc Alvarez; Emilio Castillo; Dimitrios Chasapis; Timothy Hayes 001; Luc Jaulmes; Oscar Palomar; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé; Jesús Labarta; et al. (Euro-Par, 2015)

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures. - Lluc Alvarez; Lluís Vilanova; Miquel Moretó; Marc Casas; Marc González 001; Xavier Martorell; Nacho Navarro; Eduard Ayguadé; Mateo Valero (ISCA, 2015)

Evaluating the Impact of OpenMP 4.0 Extensions on Relevant Parallel Workloads. - Raul Vidal; Marc Casas; Miquel Moretó; Dimitrios Chasapis; Roger Ferrer; Xavier Martorell; Eduard Ayguadé; Jesús Labarta; Mateo Valero (IWOMP, 2015)

Exploiting asynchrony from exact forward recovery for DUE in iterative solvers. - Luc Jaulmes; Marc Casas; Miquel Moretó; Eduard Ayguadé; Jesús Labarta; Mateo Valero (SC, 2015)

Adaptive and application dependent runtime guided hardware prefetcher reconfiguration on the IBM POWER7. - David Prat; Cristobal Ortega; Marc Casas; Miquel Moretó; Mateo Valero (CoRR, 2015)

Reducing Cache Coherence Traffic with Hierarchical Directory Cache and NUMA-Aware Runtime Scheduling. - Paul Caheny; Marc Casas; Miquel Moretó; Hervé Gloaguen; Maxime Saintes; Eduard Ayguadé; Jesús Labarta; Mateo Valero (PACT, 2016)

POSTER: Exploiting Asymmetric Multi-Core Processors with Flexible System Sofware. - Kallia Chronaki; Miquel Moretó; Marc Casas; Alejandro Rico; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (PACT, 2016)

Runtime-Guided Mitigation of Manufacturing Variability in Power-Constrained Multi-Socket NUMA Nodes. - Dimitrios Chasapis; Marc Casas; Miquel Moretó; Martin Schulz 001; Eduard Ayguadé; Jesús Labarta; Mateo Valero (ICS, 2016)

CATA: Criticality Aware Task Acceleration for Multicore Processors. - Emilio Castillo; Miquel Moretó; Marc Casas; Lluc Alvarez; Enrique Vallejo 001; Kallia Chronaki; Rosa M. Badia; José Luis Bosque; Ramón Beivide; Eduard Ayguadé; Jesús Labarta; Mateo Valero (IPDPS, 2016)

TaskPoint: Sampled simulation of task-based programs. - Thomas Grass; Alejandro Rico; Marc Casas; Miquel Moretó; Eduard Ayguadé (ISPASS, 2016)

MUSA: a multi-level simulation approach for next-generation HPC machines. - Thomas Grass; César Allande; Adrià Armejach; Alejandro Rico; Eduard Ayguadé; Jesús Labarta; Mateo Valero; Marc Casas; Miquel Moretó (SC, 2016)

PARSECSs: Evaluating the Impact of Task Parallelism in the PARSEC Benchmark Suite. - Dimitrios Chasapis; Marc Casas; Miquel Moretó; Raul Vidal; Eduard Ayguadé; Jesús Labarta; Mateo Valero (ACM Trans. Archit. Code Optim., 2016)

Sensible Energy Accounting with Abstract Metering for Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Daniel A. Jiménez; Mateo Valero (ACM Trans. Archit. Code Optim., 2016)

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach. - Petar Radojkovic; Paul M. Carpenter; Miquel Moretó; Vladimir Cakarevic; Javier Verdú; Alex Pajuelo; Francisco J. Cazorla; Mario Nemirovsky; Mateo Valero (IEEE Trans. Computers, 2016)

DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (ACM Trans. Design Autom. Electr. Syst., 2016)

Runtime-Assisted Shared Cache Insertion Policies Based on Re-reference Intervals. - Vladimir Dimic; Miquel Moretó; Marc Casas; Mateo Valero (Euro-Par, 2017)

Evaluating Scientific Workflow Execution on an Asymmetric Multicore Processor. - Ilia Pietri; Sicong Zhuang; Marc Casas; Miquel Moretó; Rizos Sakellariou (Euro-Par Workshops, 2017)

libPRISM: an intelligent adaptation of prefetch and SMT levels. - Cristobal Ortega; Miquel Moretó; Marc Casas; Ramon Bertran; Alper Buyuktosunoglu; Alexandre E. Eichenberger; Pradip Bose (ICS, 2017)

ATM: Approximate Task Memoization in the Runtime System. - Iulian Brumar; Marc Casas; Miquel Moretó; Mateo Valero; Gurindar S. Sohi (IPDPS, 2017)

iQ: An Efficient and Flexible Queue-Based Simulation Framework. - Damian Roca; Daniel Nemirovsky; Marc Casas; Miquel Moretó; Mateo Valero; Mario Nemirovsky (MASCOTS, 2017)

SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems. - Qixiao Liu; Miquel Moretó; Jaume Abella 001; Francisco J. Cazorla; Mateo Valero (SBAC-PAD, 2017)

Task Scheduling Techniques for Asymmetric Multi-Core Systems. - Kallia Chronaki; Alejandro Rico; Marc Casas; Miquel Moretó; Rosa M. Badia; Eduard Ayguadé; Jesús Labarta; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2017)

Stencil codes on a vector length agnostic architecture. - Adrià Armejach; Helena Caminal; Juan M. Cebrian; Rekai González-Alberquilla; Chris Adeniyi-Jones; Mateo Valero; Marc Casas; Miquel Moretó (PACT, 2018)

Architectural Support for Task Dependence Management with Flexible Software Scheduling. - Emilio Castillo; Lluc Alvarez; Miquel Moretó; Marc Casas; Enrique Vallejo 001; José Luis Bosque; Ramón Beivide; Mateo Valero (HPCA, 2018)

Runtime-Guided Management of Stacked DRAM Memories in Task Parallel Programs. - Lluc Alvarez; Marc Casas; Jesús Labarta; Eduard Ayguadé; Mateo Valero; Miquel Moretó (ICS, 2018)

Reducing Data Movement on Large Shared Memory Systems by Exploiting Computation Dependencies. - Isaac Sánchez Barrera; Miquel Moretó; Eduard Ayguadé; Jesús Labarta; Mateo Valero; Marc Casas (ICS, 2018)

Data Prefetching on In-order Processors. - Cristobal Ortega; Victor Garcia; Miquel Moretó; Marc Casas; Roxana Rusitoru (HPCS, 2018)

ChopStiX: Systematic Extraction of Code-Representative Microbenchmarks. - Calvin Bulla; Lluc Alvarez; Miquel Moretó; Ramon Bertran; Alper Buyuktosunoglu; Pradip Bose (IISWC, 2018)

Graph partitioning applied to DAG scheduling to reduce NUMA effects. - Isaac Sánchez Barrera; Marc Casas; Miquel Moretó; Eduard Ayguadé; Jesús Labarta; Mateo Valero (PPoPP, 2018)

Runtime-assisted cache coherence deactivation in task parallel programs. - Paul Caheny; Lluc Alvarez; Mateo Valero; Miquel Moretó; Marc Casas (SC, 2018)

TaskGenX: A Hardware-Software Proposal for Accelerating Task Parallelism. - Kallia Chronaki; Marc Casas; Miquel Moretó; Jaume Bosch; Rosa M. Badia (ISC, 2018)

Memory Vulnerability: A Case for Delaying Error Reporting. - Luc Jaulmes; Miquel Moretó; Mateo Valero; Marc Casas (CoRR, 2018)

Performance and energy effects on task-based parallelized applications - User-directed versus manual vectorization. - Helena Caminal; Diego Caballero; Juan M. Cebrian; Roger Ferrer; Marc Casas; Miquel Moretó; Xavier Martorell; Mateo Valero (J. Supercomput., 2018)

Reducing Cache Coherence Traffic with a NUMA-Aware Runtime Approach. - Paul Caheny; Lluc Alvarez; Said Derradji; Mateo Valero; Miquel Moretó; Marc Casas (IEEE Trans. Parallel Distributed Syst., 2018)

Asynchronous and Exact Forward Recovery for Detected Errors in Iterative Solvers. - Luc Jaulmes; Miquel Moretó; Eduard Ayguadé; Jesús Labarta; Mateo Valero; Marc Casas (IEEE Trans. Parallel Distributed Syst., 2018)

POSTER: SPiDRE: Accelerating Sparse Memory Access Patterns. - Adrián Barredo; Jonathan C. Beard; Miquel Moretó (PACT, 2019)

POSTER: An Optimized Predication Execution for SIMD Extensions. - Adrián Barredo; Juan M. Cebrian; Miquel Moretó; Marc Casas; Mateo Valero (PACT, 2019)

Optimizing computation-communication overlap in asynchronous task-based programs. - Emilio Castillo; Nikhil Jain; Marc Casas; Miquel Moretó; Martin Schulz 001; Ramón Beivide; Mateo Valero; Abhinav Bhatele (ICS, 2019)

Power efficient job scheduling by predicting the impact of processor manufacturing variability. - Dimitrios Chasapis; Miquel Moretó; Martin Schulz 001; Barry Rountree; Mateo Valero; Marc Casas (ICS, 2019)

A Vulnerability Factor for ECC-protected Memory. - Luc Jaulmes; Miquel Moretó; Mateo Valero; Marc Casas (IOLTS, 2019)

Design Space Exploration of Next-Generation HPC Machines. - Constantino Gómez; Francesc Martínez; Adrià Armejach; Miquel Moretó; Filippo Mantovani; Marc Casas (IPDPS, 2019)

Lagarto I RISC-V Multi-core: Research Challenges to Build and Integrate a Network-on-Chip. - Neiel I. Leyva-Santes; Ivan Perez 004; César-Alejandro Hernández-Calderón; Enrique Vallejo 001; Miquel Moretó; Ramón Beivide; Marco Antonio Ramírez Salinas; Luis A. Villa-Vargas (ISUM, 2019)

On the Benefits of Tasking with OpenMP. - Alejandro Rico; Isaac Sánchez Barrera; José A. Joao; Joshua Randall 001; Marc Casas; Miquel Moretó (IWOMP, 2019)

Optimizing computation-communication overlap in asynchronous task-based programs: poster. - Emilio Castillo; Nikhil Jain; Marc Casas; Miquel Moretó; Martin Schulz 001; Ramón Beivide; Mateo Valero; Abhinav Bhatele (PPoPP, 2019)

The international race towards Exascale in Europe. - Fabrizio Gagliardi; Miquel Moretó; Mauro Olivieri; Mateo Valero (CCF Trans. High Perform. Comput., 2019)

On the maturity of parallel applications for asymmetric multi-core processors. - Kallia Chronaki; Miquel Moretó; Marc Casas; Alejandro Rico; Rosa M. Badia; Eduard Ayguadé; Mateo Valero (J. Parallel Distributed Comput., 2019)

Sampled Simulation of Task-Based Programs. - Thomas Grass; Trevor E. Carlson; Alejandro Rico; Germán Ceballos; Eduard Ayguadé; Marc Casas; Miquel Moretó (IEEE Trans. Computers, 2019)

Design trade-offs for emerging HPC processors based on mobile market technology. - Adrià Armejach; Marc Casas; Miquel Moretó (J. Supercomput., 2019)

An Academic RISC-V Silicon Implementation Based on Open-Source Components. - Jaume Abella 001; Calvin Bulla; Guillem Cabo; Francisco J. Cazorla; Adrián Cristal; Max Doblas; Roger Figueras; Alberto González 004; Carles Hernández 001; César Hernández; Víctor Jiménez; Leonidas Kosmidis; et al. (DCIS, 2020)

A Hardware/Software Co-Design of K-mer Counting Using a CAPI-Enabled FPGA. - Abbas Haghi; Lluc Alvarez; Jordà Polo; Dionysios Diamantopoulos; Christoph Hagleitner; Miquel Moretó (FPL, 2020)

Improving Predication Efficiency through Compaction/Restoration of SIMD Instructions. - Adrián Barredo; Juan M. Cebrian; Miquel Moretó; Marc Casas; Mateo Valero (HPCA, 2020)

The DeepHealth Toolkit: A Unified Framework to Boost Biomedical Applications. - Michele Cancilla; Laura Canalini; Federico Bolelli; Stefano Allegretti; Salvador Carrión; Roberto Paredes; Jon Ander Gómez; Simone Leo; Marco Enrico Piras; Luca Pireddu; Asaf Badouh; Santiago Marco-Sola; et al. (ICPR, 2020)

Modeling and optimizing NUMA effects and prefetching with machine learning. - Isaac Sánchez Barrera; David Black-Schaffer; Marc Casas; Miquel Moretó; Anastasiia Stupnikova; Mihail Popov (ICS, 2020)

RICH: implementing reductions in the cache hierarchy. - Vladimir Dimic; Miquel Moretó; Marc Casas; Jan Ciesko; Mateo Valero (ICS, 2020)

BST: A BookSim-Based Toolset to Simulate NoCs with Single- and Multi-Hop Bypass. - Ivan Perez 004; Enrique Vallejo 001; Miquel Moretó; Ramón Beivide (ISPASS, 2020)

Runtime-guided ECC protection using online estimation of memory vulnerability. - Luc Jaulmes; Miquel Moretó; Mateo Valero; Mattan Erez; Marc Casas (SC, 2020)

Semi-automatic validation of cycle-accurate simulation infrastructures: The case for gem5-x86. - Juan M. Cebrian; Adrián Barredo; Helena Caminal; Miquel Moretó; Marc Casas; Mateo Valero (Future Gener. Comput. Syst., 2020)

Using Arm's scalable vector extension on stencil codes. - Adrià Armejach; Helena Caminal; Juan M. Cebrian; Rubén Langarita; Rekai González-Alberquilla; Chris Adeniyi-Jones; Mateo Valero; Marc Casas; Miquel Moretó (J. Supercomput., 2020)

Efficiency analysis of modern vector architectures: vector ALU sizes, core counts and clock frequencies. - Adrián Barredo; Juan M. Cebrian; Mateo Valero; Marc Casas; Miquel Moretó (J. Supercomput., 2020)

Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. - Adrià Armejach; Bine Brank; Jordi Cortina; François Dolique; Timothy Hayes 001; Nam Ho; Pierre-Axel Lagadec; Romain Lemaire; Guillem López-Paradís; Laurent Marliac; Miquel Moretó; Pedro Marcuello; et al. (DATE, 2021)

SafeSU: an Extended Statistics Unit for Multicore Timing Interference. - Guillem Cabo; Francisco Bas; Ruben Lorenzo; David Trilla; Sergi Alcaide; Miquel Moretó; Carles Hernández 001; Jaume Abella 001 (ETS, 2021)

PrioRAT: Criticality-Driven Prioritization Inside the On-Chip Memory Hierarchy. - Vladimir Dimic; Miquel Moretó; Marc Casas; Mateo Valero (Euro-Par, 2021)

OpenCL-based FPGA Accelerator for Semi-Global Approximate String Matching Using Diagonal Bit-Vectors. - David Castells-Rufas; Santiago Marco-Sola; Quim Aguado-Puig; Antonio Espinosa-Morales; Juan Carlos Moure; Lluc Alvarez; Miquel Moretó (FPL, 2021)

An FPGA Accelerator of the Wavefront Algorithm for Genomics Pairwise Alignment. - Abbas Haghi; Santiago Marco-Sola; Lluc Alvarez; Dionysios Diamantopoulos; Christoph Hagleitner; Miquel Moretó (FPL, 2021)

HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem. - Vatistas Kostalabros; Jordi Ribes-González; Oriol Farràs; Miquel Moretó; Carles Hernández 001 (FPL, 2021)

VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations. - Julian Pavon; Iván Vargas Valdivieso; Adrián Barredo; Joan Marimon; Miquel Moretó; Francesc Moll; Osman S. Unsal; Mateo Valero; Adrián Cristal (HPCA, 2021)

gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator. - Guillem López-Paradís; Adrià Armejach; Miquel Moretó (ICPP, 2021)

PLANAR: a programmable accelerator for near-memory data rearrangement. - Adrián Barredo; Adrià Armejach; Jonathan C. Beard; Miquel Moretó (ICS, 2021)

PIugSMART: a pluggable open-source module to implement multihop bypass in networks-on-chip. - Alireza Monemi; Iván Pérez 004; Neiel Leyva; Enrique Vallejo 001; Ramón Beivide; Miquel Moretó (NOCS, 2021)

Intelligent Adaptation of Hardware Knobs for Improving Performance and Power Consumption. - Cristobal Ortega; Lluc Alvarez; Marc Casas; Ramon Bertran; Alper Buyuktosunoglu; Alexandre E. Eichenberger; Pradip Bose; Miquel Moretó (IEEE Trans. Computers, 2021)

On the use of many-core Marvell ThunderX2 processor for HPC workloads. - Víctor Soria Pardos; Adrià Armejach; Darío Suárez Gracia; Miquel Moretó (J. Supercomput., 2021)

Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs. - Tim Hotfilter; Fabian Kreß; Fabian Kempf; Jürgen Becker 001; Juan Miguel De Haro Ruiz; Daniel Jiménez-González; Miquel Moretó; Carlos Álvarez 001; Jesús Labarta; Imen Baili (DATE, 2022)

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology. - Guillem Cabo; Gerard Candón; Xavier Carril; Max Doblas; Marc Domínguez; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2022)

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI. - Víctor Soria Pardos; Max Doblas; Guillem López-Paradís; Gerard Candón; Narcís Rodas; Xavier Carril; Pau Fontova-Musté; Neiel Leyva; Santiago Marco-Sola; Miquel Moretó (DSD, 2022)

TD-NUCA: Runtime Driven Management of NUCA Caches in Task Dataflow Programming Models. - Paul Caheny; Lluc Alvarez; Marc Casas; Miquel Moretó (SC, 2022)

Accelerating Edit-Distance Sequence Alignment on GPU Using the Wavefront Algorithm. - Quim Aguado-Puig; Santiago Marco-Sola; Juan Carlos Moure; David Castells-Rufas; Lluc Alvarez; Antonio Espinosa 001; Miquel Moretó (IEEE Access, 2022)

Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. - Rubén Langarita; Adrià Armejach; Javier Setoain; Pablo Ibáñez-Marín; Jesús Alastruey-Benedé; Miquel Moretó (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

A Security Model for Randomization-based Protected Caches. - Jordi Ribes-González; Oriol Farràs; Carles Hernández 001; Vatistas Kostalabros; Miquel Moretó (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022)

Compiler-Assisted Compaction/Restoration of SIMD Instructions. - Juan M. Cebrian; Thibaud Balem; Adrián Barredo; Marc Casas; Miquel Moretó; Alberto Ros 001; Alexandra Jimborean (IEEE Trans. Parallel Distributed Syst., 2022)

Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi. - Guillem López-Paradís; Brian Li; Adrià Armejach; Stefan Wallentowitz; Miquel Moretó; Jonathan Balkind (DATE, 2023)

Sargantana: An Academic SoC RISC-V Processor in 22nm FDSOI Technology. - Max Doblas; Gerard Candón; Xavier Carril; Marc Domínguez; Enric Erra; Alberto González 004; César Hernández; Víctor Jiménez; Vatistas Kostalampros; Rubén Langarita; Neiel Leyva; Guillem López-Paradís; et al. (DCIS, 2023)

RISC-V for Genome Data Analysis: Opportunities and Challenges. - Lorién López-Villellas; Esteve Pineda-Sánchez; Asaf Badouh; Santiago Marco-Sola; Pablo Ibáñez 001; Jesús Alastruey-Benedé; Miquel Moretó (DCIS, 2023)

Mix-GEMM: An efficient HW-SW Architecture for Mixed-Precision Quantized Deep Neural Networks Inference on Edge Devices. - Enrico Reggiani; Alessandro Pappalardo; Max Doblas; Miquel Moretó; Mauro Olivieri; Osman Sabri Unsal; Adrián Cristal (HPCA, 2023)

WFAsic: A High-Performance ASIC Accelerator for DNA Sequence Alignment on a RISC-V SoC. - Abbas Haghi; Lluc Alvarez; Jordi Fornt; Juan Miguel De Haro Ruiz; Roger Figueras; Max Doblas; Santiago Marco-Sola; Miquel Moretó (ICPP, 2023)

DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations. - Víctor Soria Pardos; Adrià Armejach; Tiago Mück; Darío Suárez Gracia; José A. Joao; Alejandro Rico; Miquel Moretó (ISCA, 2023)

GMX: Instruction Set Extensions for Fast, Scalable, and Efficient Genome Sequence Alignment. - Max Doblas; Oscar Lostes-Cazorla; Quim Aguado-Puig; Nick Cebry; Pau Fontova-Musté; Christopher Frances Batten; Santiago Marco-Sola; Miquel Moretó (MICRO, 2023)

OpenPiton Optimizations Towards High Performance Manycores. - Neiel Leyva; Alireza Monemi; Noelia Oliete-Escuín; Guillem López-Paradís; Xabier Abancens; Jonathan Balkind; Enrique Vallejo 001; Miquel Moretó; Lluc Alvarez (NoCArc@MICRO, 2023)

A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors. - Marco Siracusa; Víctor Soria Pardos; Francesco Sgherzi; Joshua Randall 001; Douglas J. Joseph; Miquel Moretó Planas; Adrià Armejach (MICRO, 2023)

Characterization of a Coherent Hardware Accelerator Framework for SoCs. - Guillem López-Paradís; Balaji Venu; Adrià Armejach; Miquel Moretó (SAMOS, 2023)

Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor. - Rubén Langarita; Adrià Armejach; Pablo Ibáñez 001; Jesús Alastruey-Benedé; Miquel Moretó (IEEE ACM Trans. Comput. Biol. Bioinform., 2023)

Optimal gap-affine alignment in O(s) space. - Santiago Marco-Sola; Jordan M. Eizenga; Andrea Guarracino; Benedict Paten; Erik Garrison; Miquel Moretó (Bioinform., 2023)

Adaptive Power Shifting for Power-Constrained Heterogeneous Systems. - Cristobal Ortega; Lluc Alvarez; Alper Buyuktosunoglu; Ramon Bertran; Todd Rosedahl; Pradip Bose; Miquel Moretó (IEEE Trans. Computers, 2023)

Functional Verification of a RISC-V Vector Accelerator. - Víctor Jiménez; Mario Rodríguez; Marc Domínguez; Josep Sans; Ivan Diaz; Luca Valente; Vito Luca Guglielmi; Josue V. Quiroga; R. Ignacio Genovese; Nehir Sönmez; Oscar Palomar; Miquel Moretó (IEEE Des. Test, 2023)

Accurate and efficient constrained molecular dynamics of polymers using Newton's method and special purpose code. - Lorién López-Villellas; Carl Christian Kjelgaard Mikkelsen; Juan José Galano-Frutos; Santiago Marco-Sola; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Miquel Moretó; Javier Sancho; Pablo García-Risueño (Comput. Phys. Commun., 2023)

WFA-GPU: gap-affine pairwise read-alignment using GPUs. - Quim Aguado-Puig; Max Doblas; Christos Matzoros; Antonio Espinosa 001; Juan Carlos Moure; Santiago Marco-Sola; Miquel Moretó (Bioinform., 2023)

Special Issue on the 2023 International Symposium on Networks-on-Chip (NOCS 2023). - Mahdi Nikdast; Miquel Moretó; Masoumeh Ebrahimi; Sujay Deb (IEEE Des. Test, 2023)

WFA-FPGA: An efficient accelerator of the wavefront algorithm for short and long read genomics alignment. - Abbas Haghi; Santiago Marco-Sola; Lluc Alvarez; Dionysios Diamantopoulos; Christoph Hagleitner; Miquel Moretó (Future Gener. Comput. Syst., 2023)

A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator. - Vatistas Kostalabros; Jordi Ribes-González; Oriol Farràs; Miquel Moretó; Carles Hernández 001 (ARC, 2024)

3D Decision Support Tool for Brain Tumour Surgery: The STRATUM Project. - Himar Fabelo; Raquel León; Emanuele Torti; Santiago Marco; Max Verbers; Yann Falevoz; Yolanda Ramallo-Fariña; Christian Weis; Ana M. Wägner; Eduardo Juárez Martínez; Claudio Rial; Alfonso Lagares; et al. (DSD, 2024)

A Mess of Memory System Benchmarking, Simulation and Application Profiling. - Pouya Esmaili-Dokht; Francesco Sgherzi; Valéria Soldera Girelli; Isaac Boixaderas; Mariana Carmin; Alireza Monemi; Adrià Armejach; Estanislao Mercadal; Germán Llort; Petar Radojkovic; Miquel Moretó; Judit Giménez; et al. (MICRO, 2024)

Floating Point HUB Adder for RISC-V Sargantana Processor. - Gerardo Bandera; Javier Salamero; Miquel Moretó; Julio Villalba (CoRR, 2024)

A Mess of Memory System Benchmarking, Simulation and Application Profiling. - Pouya Esmaili-Dokht; Francesco Sgherzi; Valéria Soldera Girelli; Isaac Boixaderas; Mariana Carmin; Alireza Momeni; Adrià Armejach; Estanislao Mercadal; Germán Llort; Petar Radojkovic; Miquel Moretó; Judit Giménez; et al. (CoRR, 2024)

GenArchBench: A genomics benchmark suite for arm HPC processors. - Lorién López-Villellas; Rubén Langarita-Benítez; Asaf Badouh; Víctor Soria Pardos; Quim Aguado-Puig; Guillem López-Paradís; Max Doblas; Javier Setoain; Chulho Kim; Makoto Ono; Adrià Armejach; Santiago Marco-Sola; et al. (Future Gener. Comput. Syst., 2024)

SpChar: Characterizing the sparse puzzle via decision trees. - Francesco Sgherzi; Marco Siracusa; Ivan Fernandez; Adrià Armejach; Miquel Moretó (J. Parallel Distributed Comput., 2024)

OpenPiton4HPC: Optimizing OpenPiton Toward High-Performance Manycores. - Neiel Leyva; Alireza Monemi; Noelia Oliete-Escuín; Guillem López-Paradís; Xabier Abancens; Jonathan Balkind; Enrique Vallejo 001; Miquel Moretó; Lluc Alvarez (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium. - Xavier Carril; Charalampos Kardaris; Jordi Ribes-González; Oriol Farràs; Carles Hernández 001; Vatistas Kostalabros; Joel Ulises González-Jiménez; Miquel Moretó (ACM Trans. Reconfigurable Technol. Syst., 2024)

ILVES: Accurate and efficient bond length and angle constraints in molecular dynamics. - Lorién López-Villellas; Carl Christian Kjelgaard Mikkelsen; Juan José Galano-Frutos; Santiago Marco-Sola; Jesús Alastruey-Benedé; Pablo Ibáñez 001; Miquel Moretó; Maria Cristina De Rosa; Pablo García-Risueño (CoRR, 2025)

TuRTLe: A Unified Evaluation of LLMs for RTL Generation. - Dario Garcia-Gasulla; Gokcen Kestor; Emanuele Parisi; Miquel Albert'i-Binimelis; Cristian Gutierrez; Razine Moundir Ghorab; Orlando Montenegro; Bernat Homs; Miquel Moretó (CoRR, 2025)

Empowering Vector Architectures for ML: The CAMP Architecture for Matrix Multiplication. - Mohammadreza Esmali Nojehdeh; Hossein Mokhtarnia; Julian Pavon Rivera; Narcis Rodas Quiroga; Roger Figueras Bagué; Enrico Reggiani; Miquel Moretó; Osman S. Unsal; Adrián Cristal; Eduard Ayguadé (CoRR, 2025)

Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures. - Marco Siracusa; Olivia Hsu; Víctor Soria Pardos; Joshua Randall 001; Arnaud Grasset; Eric Biscondi; Douglas J. Joseph; Randy Allen; Fredrik Kjolstad; Miquel Moretó Planas; Adrià Armejach (CoRR, 2025)