Power-Performance Trade-Offs in Wide and Clustered VLIW Cores for Numerical Codes. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (ISHPC, 2003)

An Optimized Front-End Physical Register File with Banking and Writeback Filtering. - Miquel Pericàs; Rubén González 001; Adrián Cristal; Alexander V. Veidenbaum; Mateo Valero (PACS, 2004)

Performance and Power Evaluation of Clustered VLIW Processors with Wide Functional Units. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (SAMOS, 2004)

High-performance and low-power VLIW cores for numerical computations. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (Int. J. High Perform. Comput. Netw., 2004)

An asymmetric clustered processor based on value content. - Rubén González 001; Adrián Cristal; Miquel Pericàs; Mateo Valero; Alexander V. Veidenbaum (ICS, 2005)

Exploiting Execution Locality with a Decoupled Kilo-Instruction Processor. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez; Mateo Valero (ISHPC, 2005)

Decoupled State-Execute Architecture. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Alexander V. Veidenbaum; Mateo Valero (ISHPC, 2005)

Chained In-Order/Out-of-Order DoubleCore Architecture. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez (SBAC-PAD, 2005)

Kilo-Instruction Processors: Overcoming the Memory Wall. - Adrián Cristal; Oliverio J. Santana; Francisco J. Cazorla; Marco Galluzzi; Tanausú Ramírez; Miquel Pericàs; Mateo Valero (IEEE Micro, 2005)

A decoupled KILO-instruction processor. - Miquel Pericàs; Adrián Cristal; Rubén González 001; Daniel A. Jiménez; Mateo Valero (HPCA, 2006)

A Flexible Heterogeneous Multi-Core Architecture. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Daniel A. Jiménez; Mateo Valero (PACT, 2007)

A Two-Level Load/Store Queue Based on Execution Locality. - Miquel Pericàs; Adrián Cristal; Francisco J. Cazorla; Rubén González 001; Alexander V. Veidenbaum; Daniel A. Jiménez; Mateo Valero (ISCA, 2008)

Vectorized AES Core for High-throughput Secure Environments. - Miquel Pericàs; Ricardo Chaves; Georgi Gaydadjiev; Stamatis Vassiliadis; Mateo Valero (VECPAR, 2008)

Power-efficient VLIW design using clustering and widening. - Miquel Pericàs; Eduard Ayguadé; Javier Zalamea; Josep Llosa; Mateo Valero (Int. J. Embed. Syst., 2008)

Affordable kilo-instruction processors. - Miquel Pericàs (2008)

Exploiting memory customization in FPGA for 3D stencil computations. - Muhammad Shafiq 003; Miquel Pericàs; Raúl de la Cruz; Mauricio Araya-Polo; Nacho Navarro; Eduard Ayguadé (FPT, 2009)

FEM: A Step Towards a Common Memory Layout for FPGA Based Accelerators. - Muhammad Shafiq 003; Miquel Pericàs; Nacho Navarro; Eduard Ayguadé (FPL, 2010)

Implementation of a Reverse Time Migration kernel using the HCE High Level Synthesis tool. - Tassadaq Hussain; Miquel Pericàs; Nacho Navarro; Eduard Ayguadé (FPT, 2011)

TARCAD: A template architecture for reconfigurable accelerator designs. - Muhammad Shafiq 003; Miquel Pericàs; Nacho Navarro; Eduard Ayguadé (SASP, 2011)

Implementation of a hierarchical N-body simulator using the Ompss programming model. - Miquel Pericàs; Xavier Martorell; Yoav Etsion (IA3@SC, 2011)

Assessing Accelerator-Based HPC Reverse Time Migration. - Mauricio Araya-Polo; Javier Cabezas; Mauricio Hanzich; Miquel Pericàs; Félix Rubio; Isaac Gelado; Muhammad Shafiq 003; Enric Morancho; Nacho Navarro; Eduard Ayguadé; José María Cela; Mateo Valero (IEEE Trans. Parallel Distributed Syst., 2011)

PPMC: A Programmable Pattern Based Memory Controller. - Tassadaq Hussain; Muhammad Shafiq 003; Miquel Pericàs; Nacho Navarro; Eduard Ayguadé (ARC, 2012)

BSArc: blacksmith streaming architecture for HPC accelerators. - Muhammad Shafiq 003; Miquel Pericàs; Nacho Navarro; Eduard Ayguadé (Conf. Computing Frontiers, 2012)

PPMC: Hardware scheduling and memory management support for multi accelerators. - Tassadaq Hussain; Miquel Pericàs; Nacho Navarro; Eduard Ayguadé (FPL, 2012)

Assessing the Impact of Network Compression on Molecular Dynamics and Finite Element Methods. - Branimir Dickov; Miquel Pericàs; Guillaume Houzeaux; Nacho Navarro; Eduard Ayguadé (HPCC-ICESS, 2012)

Analysis of Data Reuse in Task-Parallel Runtimes. - Miquel Pericàs; Abdelhalim Amer; Kenjiro Taura; Satoshi Matsuoka (PMBS@SC, 2013)

Fork-Join and Data-Driven Execution Models on Multi-core Architectures: Case Study of the FMM. - Abdelhalim Amer; Naoya Maruyama; Miquel Pericàs; Kenjiro Taura; Rio Yokota; Satoshi Matsuoka (ISC, 2013)

A template system for the efficient compilation of domain abstractions onto reconfigurable computers. - Muhammad Shafiq 003; Miquel Pericàs; Nacho Navarro; Eduard Ayguadé (J. Syst. Archit., 2013)

Guest editorial: Workshop on Reconfigurable Computing. - Ioannis Sourdis; Christos-Savvas Bouganis; Miquel Pericàs (J. Syst. Archit., 2013)

Efficient String Sorting on Multi - and Many-Core Architectures. - Aleksandr Drozd; Miquel Pericàs; Satoshi Matsuoka (BigData Congress, 2014)

Software-Managed Power Reduction in Infiniband Links. - Branimir Dickov; Miquel Pericàs; Paul M. Carpenter; Nacho Navarro; Eduard Ayguadé (ICPP, 2014)

Scalable analysis of multicore data reuse and sharing. - Miquel Pericàs; Kenjiro Taura; Satoshi Matsuoka (ICS, 2014)

Analyzing Performance Improvements and Energy Savings in Infiniband Architecture using Network Compression. - Branimir Dickov; Miquel Pericàs; Paul M. Carpenter; Nacho Navarro; Eduard Ayguadé (SBAC-PAD, 2014)

Self-Tuned Software-Managed Energy Reduction in InfiniBand Links. - Branimir Dickov; Paul M. Carpenter; Miquel Pericàs; Eduard Ayguadé (ICPADS, 2015)

DAGViz: a DAG visualization tool for analyzing task-parallel program traces. - An Huynh; Douglas Thain; Miquel Pericàs; Kenjiro Taura (VPA@SC, 2015)

POSTER: ξ-TAO: A Cache-centric Execution Model and Runtime for Deep Parallel Multicore Topologies. - Miquel Pericàs (PACT, 2016)

RADAR: Runtime-assisted dead region management for last-level caches. - Madhavan Manivannan; Vassilis Papaefstathiou; Miquel Pericàs; Per Stenström (HPCA, 2016)

Scaling FMM with Data-Driven OpenMP Tasks on Multicore Architectures. - Abdelhalim Amer; Satoshi Matsuoka; Miquel Pericàs; Naoya Maruyama; Kenjiro Taura; Rio Yokota; Pavan Balaji (IWOMP, 2016)

SWAS: Stealing Work Using Approximate System-Load Information. - Stavros Tzilis; Miquel Pericàs; Pedro Trancoso; Ioannis Sourdis (ICPP Workshops, 2017)

Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. - Madhavan Manivannan; Miquel Pericàs; Vassilis Papaefstathiou; Per Stenström (IEEE Comput. Archit. Lett., 2017)

Trends in Data Locality Abstractions for HPC Systems. - Didem Unat; Anshu Dubey; Torsten Hoefler; John Shalf; Mark James Abraham; Mauro Bianco; Bradford L. Chamberlain; Romain Cledat; H. Carter Edwards; Hal Finkel; Karl Fuerlinger; Frank Hannig; et al. (IEEE Trans. Parallel Distributed Syst., 2017)

LEGaTO: towards energy-efficient, secure, fault-tolerant toolset for heterogeneous computing. - Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel Jiménez-González; Carlos Álvarez 001; Behzad Salami 001; Sergi Madonar; Miquel Pericàs; Pedro Trancoso; et al. (CF, 2018)

LEGaTO: first steps towards energy-efficient toolset for heterogeneous computing. - Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel Jiménez-González; Carlos Álvarez 001; Behzad Salami 001; Sergi Madonar; Miquel Pericàs; Pedro Trancoso; et al. (SAMOS, 2018)

Global Dead-Block Management for Task-Parallel Programs. - Madhavan Manivannan; Miquel Pericàs; Vassilis Papaefstathiou; Per Stenström (ACM Trans. Archit. Code Optim., 2018)

Elastic Places: An Adaptive Resource Manager for Scalable and Portable Performance. - Miquel Pericàs (ACM Trans. Archit. Code Optim., 2018)

SaC: Exploiting Execution-Time Slack to Save Energy in Heterogeneous Multicore Systems. - Muhammad Waqar Azhar; Miquel Pericàs; Per Stenström (ICPP, 2019)

QoS-Driven Coordinated Management of Resources to Save Energy in Multi-core Systems. - Mehrzad Nejat; Miquel Pericàs; Per Stenström (IPDPS, 2019)

High performance scheduling of mixed-mode DAGs on heterogeneous multicores. - Agnes Rohlin; Henrik Fahlgren; Miquel Pericàs (CoRR, 2019)

An Adaptive Performance-oriented Scheduler for Static and Dynamic Heterogeneity. - Jing Chen 038; Pirah Noor Soomro; Mustafa Abdul Jabbar; Miquel Pericàs (CoRR, 2019)

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. - Behzad Salami 001; Konstantinos Parasyris; Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel A. Jiménez; Carlos Álvarez 001; S. Nabavi; Sergi Madonar; et al. (CoRR, 2019)

Enhancing Thread-Level Parallelism in Asymmetric Multicores using Transparent Instruction Offloading. - Jeckson Dellagostin Souza; Madhavan Manivannan; Miquel Pericàs; Antonio Carlos Schneider Beck (DAC, 2020)

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing. - Behzad Salami 001; Konstantinos Parasyris; Adrián Cristal; Osman S. Unsal; Xavier Martorell; Paul Carpenter; Raúl de la Cruz; Leonardo Bautista-Gomez; Daniel A. Jiménez; Carlos Álvarez 001; Seyed Saber Nabavi Larimi; Sergi Madonar; et al. (DATE, 2020)

Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD Offloading. - Jeckson Dellagostin Souza; Madhavan Manivannan; Miquel Pericàs; Antonio Carlos Schneider Beck (DATE, 2020)

Scheduling Task-parallel Applications in Dynamically Asymmetric Environments. - Jing Chen 038; Pirah Noor Soomro; Mustafa Abduljabbar; Madhavan Manivannan; Miquel Pericàs (ICPP Workshops, 2020)

DELTA: Distributed Locality-Aware Cache Partitioning for Tile-based Chip Multiprocessors. - Nadja Holtryd; Madhavan Manivannan; Per Stenström; Miquel Pericàs (IPDPS, 2020)

Coordinated Management of Processor Configuration and Cache Partitioning to Optimize Energy under QoS Constraints. - Mehrzad Nejat; Madhavan Manivannan; Miquel Pericàs; Per Stenström (IPDPS, 2020)

Proceedings of the Thirteenth International Workshop on Programmability and Architectures for Heterogeneous Multicores (MULTIPROG-2020). - Miquel Pericàs; Oscar Palomar; Vassilis Papaefstathiou; Mahmoud Eljammaly (CoRR, 2020)

Coordinated management of DVFS and cache partitioning under QoS constraints to save energy in multi-core systems. - Mehrzad Nejat; Madhavan Manivannan; Miquel Pericàs; Per Stenström (J. Parallel Distributed Comput., 2020)

CBP: Coordinated management of cache partitioning, bandwidth partitioning and prefetch throttling. - Nadja Ramhöj Holtryd; Madhavan Manivannan; Per Stenström; Miquel Pericàs (PACT, 2021)

An online guided tuning approach to run CNN pipelines on edge devices. - Pirah Noor Soomro; Mustafa Abduljabbar; Jerónimo Castrillón; Miquel Pericàs (CF, 2021)

Vectorized Barrier and Reduction in LLVM OpenMP Runtime. - Muhammed Nufail Farooqi; Miquel Pericàs (IWOMP, 2021)

Mitigating inefficient task mappings with an Adaptive Resource-Moldable Scheduler (ARMS). - Mustafa Abduljabbar; Mahmoud Eljammaly; Miquel Pericàs (CoRR, 2021)

Shisha: Online Scheduling of CNN Pipelines on Heterogeneous Architectures. - Pirah Noor Soomro; Mustafa Abduljabbar; Jerónimo Castrillón; Miquel Pericàs (PPAM (1), 2022)

STEER: Asymmetry-aware Energy Efficient Task Scheduler for Cluster-based Multicore Architectures. - Jing Chen 038; Madhavan Manivannan; Bhavishya Goel; Mustafa Abduljabbar; Miquel Pericàs (SBAC-PAD, 2022)

At the Locus of Performance: A Case Study in Enhancing CPUs with Copious 3D-Stacked Cache. - Jens Domke; Emil Vatai; Balazs Gerofi; Yuetsu Kodama; Mohamed Wahib; Artur Podobas; Sparsh Mittal; Miquel Pericàs; Lingqi Zhang 001; Peng Chen 035; Aleksandr Drozd; Satoshi Matsuoka (CoRR, 2022)

Energy-Efficiency Evaluation of OpenMP Loop Transformations and Runtime Constructs. - Henrik Valter; Axel Karlsson; Miquel Pericàs (CoRR, 2022)

Task-RM: A Resource Manager for Energy Reduction in Task-Parallel Applications under Quality of Service Constraints. - Muhammad Waqar Azhar; Miquel Pericàs; Per Stenström (ACM Trans. Archit. Code Optim., 2022)

ERASE: Energy Efficient Task Mapping and Resource Management for Work Stealing Runtimes. - Jing Chen 038; Madhavan Manivannan; Mustafa Abduljabbar; Miquel Pericàs (ACM Trans. Archit. Code Optim., 2022)

Cooperative Slack Management: Saving Energy of Multicore Processors by Trading Performance Slack Between QoS-Constrained Applications. - Mehrzad Nejat; Madhavan Manivannan; Miquel Pericàs; Per Stenström (ACM Trans. Archit. Code Optim., 2022)

ODIN: Overcoming Dynamic Interference in iNference Pipelines. - Pirah Noor Soomro; Nikela Papadopoulou; Miquel Pericàs (Euro-Par, 2023)

JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. - Jing Chen 038; Madhavan Manivannan; Bhavishya Goel; Miquel Pericàs (ICPP, 2023)

Accelerating CNN inference on long vector architectures via co-design. - Sonia Rani Gupta; Nikela Papadopoulou; Miquel Pericàs (IPDPS, 2023)

Analysis and Characterization of Performance Variability for OpenMP Runtime. - Minyu Cui; Nikela Papadopoulou; Miquel Pericàs (SC Workshops, 2023)

Challenges and Opportunities in the Co-design of Convolutions and RISC-V Vector Processors. - Sonia Rani Gupta; Nikela Papadopoulou; Miquel Pericàs (SC Workshops, 2023)

JOSS: Joint Exploration of CPU-Memory DVFS and Task Scheduling for Energy Efficiency. - Jing Chen; Madhavan Manivannan; Bhavishya Goel; Miquel Pericàs (CoRR, 2023)

At the Locus of Performance: Quantifying the Effects of Copious 3D-Stacked Cache on HPC Workloads. - Jens Domke; Emil Vatai; Balazs Gerofi; Yuetsu Kodama; Mohamed Wahib; Artur Podobas; Sparsh Mittal; Miquel Pericàs; Lingqi Zhang 001; Peng Chen 035; Aleksandr Drozd; Satoshi Matsuoka (ACM Trans. Archit. Code Optim., 2023)

Co-Design of Convolutional Algorithms and Long Vector RISC-V Processors for Efficient CNN Model Serving. - Sonia Rani Gupta; Nikela Papadopoulou; Jing Chen 038; Miquel Pericàs (ICPP, 2024)

SWEEP: Adaptive Task Scheduling for Exploring Energy Performance Trade-offs. - Jing Chen 038; Madhavan Manivannan; Bhavishya Goel; Miquel Pericàs (IPDPS, 2024)

Characterizing and Mitigating Performance Variability in Parallel Applications on Modern HPC multicore Systems. - Minyu Cui; Miquel Pericàs (CF, 2025)

Accordion: A malleable pipeline scheduling approach for adaptive SLO-aware inference serving. - Pirah Noor Soomro; Nikela Papadopoulou; Miquel Pericàs (CF, 2025)

CNN and RVV Co-design for Efficient Model Serving. - Sonia Rani Gupta; Nikela Papadopoulou; Jing Chen 038; Miquel Pericàs (DEBS, 2025)

Evaluation and Mitigation of Performance Variability of OpenMP Applications on Modern Multicore Systems. - Minyu Cui; Miquel Pericàs (IPDPS (Workshops), 2025)

Exploring SYCL as a Portability Layer for High-Performance Computing on CPUs. - Hari Abram; Nikela Papadopoulou; Miquel Pericàs (ISC, 2025)