Analyzing On-Chip Communication in a MPSoC Environment. - Mirko Loghi; Federico Angiolini; Davide Bertozzi; Luca Benini; Roberto Zafalon (DATE, 2004)

Cycle-accurate power analysis for multiprocessor systems-on-a-chip. - Mirko Loghi; Massimo Poncino; Luca Benini (ACM Great Lakes Symposium on VLSI, 2004)

Analyzing Power Consumption of Message Passing Primitives in a Single-Chip Multiprocessor. - Mirko Loghi; Luca Benini; Massimo Poncino (ICCD, 2004)

Virtual Hardware Prototyping through Timed Hardware-Software Co-Simulation. - Franco Fummi; Mirko Loghi; Stefano Martini; Marco Monguzzi; Giovanni Perbellini; Massimo Poncino (DATE, 2005)

Tag Overflow Buffering: An Energy-Efficient Cache Architecture. - Mirko Loghi; Paolo Azzoni; Massimo Poncino (DATE, 2005)

Exploring Energy/Performance Tradeoffs in Shared Memory MPSoCs: Snoop-Based Cache Coherence vs. Software Solutions. - Mirko Loghi; Massimo Poncino (DATE, 2005)

Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. - Mirko Loghi; Martin Letis; Luca Benini; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2005)

Dynamic and Formal Verification of Embedded Systems: A Comparative Survey. - Mirko Loghi; Tiziana Margaria; Graziano Pravadelli; Bernhard Steffen (Int. J. Parallel Program., 2005)

ISS-centric modular HW/SW co-simulation. - Franco Fummi; Giovanni Perbellini; Mirko Loghi; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2006)

Synchronization-driven dynamic speed scaling for MPSoCs. - Mirko Loghi; Massimo Poncino; Luca Benini (ISLPED, 2006)

Cache coherence tradeoffs in shared-memory MPSoCs. - Mirko Loghi; Massimo Poncino; Luca Benini (ACM Trans. Embed. Comput. Syst., 2006)

Architectural leakage-aware management of partitioned scratchpad memories. - Olga Golubeva; Mirko Loghi; Massimo Poncino; Enrico Macii (DATE, 2007)

On the energy efficiency of synchronization primitives for shared-memory single-chip multiprocessors. - Olga Golubeva; Mirko Loghi; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2007)

Locality-driven architectural cache sub-banking for leakage energy reduction. - Olga Golubeva; Mirko Loghi; Enrico Macii; Massimo Poncino (ISLPED, 2007)

SystemC co-simulation for core-based embedded systems. - Franco Fummi; Mirko Loghi; Giovanni Perbellini; Massimo Poncino (Des. Autom. Embed. Syst., 2007)

Energy-Efficient Multiprocessor Systems-on-Chip for Embedded Computing: Exploring Programming Models and Their Architectural Support. - Francesco Poletti; Antonio Poggiali; Davide Bertozzi; Luca Benini; Pol Marchal; Mirko Loghi; Massimo Poncino (IEEE Trans. Computers, 2007)

Power macromodeling of MPSoC message passing primitives. - Mirko Loghi; Luca Benini; Massimo Poncino (ACM Trans. Embed. Comput. Syst., 2007)

Energy-optimal synchronization primitives for single-chip multi-processors. - Cesare Ferri; R. Iris Bahar; Mirko Loghi; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2009)

A cosimulation methodology for HW/SW validation and performance estimation. - Franco Fummi; Mirko Loghi; Massimo Poncino; Graziano Pravadelli (ACM Trans. Design Autom. Electr. Syst., 2009)

Tag Overflow Buffering: Reducing Total Memory Energy by Reduced-Tag Matching. - Mirko Loghi; Paolo Azzoni; Massimo Poncino (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Aging effects of leakage optimizations for caches. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2010)

Dynamic indexing: concurrent leakage and aging optimization for caches. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (ISLPED, 2010)

Architectural Leakage Power Minimization of Scratchpad Memories by Application-Driven Subbanking. - Mirko Loghi; Olga Golubeva; Enrico Macii; Massimo Poncino (IEEE Trans. Computers, 2010)

Partitioned cache architectures for reduced NBTI-induced aging. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (DATE, 2011)

Buffering of frequent accesses for reduced cache aging. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2011)

Application-specific memory partitioning for joint energy and lifetime optimization. - Haroon Mahmood; Massimo Poncino; Mirko Loghi; Enrico Macii (DATE, 2012)

Energy-optimal caches with guaranteed lifetime. - Mirko Loghi; Haroon Mahmood; Andrea Calimera; Massimo Poncino; Enrico Macii (ISLPED, 2012)

Aging-aware caches with graceful degradation of performance. - Haroon Mahmood; Massimo Poncino; Mirko Loghi; Enrico Macii (VLSI-SoC, 2012)

Firefly-Inspired Synchronization of Sensor Networks with Variable Period Lengths. - Stefan Wieser; Pier Luca Montessoro; Mirko Loghi (ICANNGA, 2013)

Dynamic Indexing: Leakage-Aging Co-Optimization for Caches. - Andrea Calimera; Mirko Loghi; Enrico Macii; Massimo Poncino (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Energy/Lifetime Cooptimization by Cache Partitioning With Graceful Performance Degradation. - Haroon Mahmood; Mirko Loghi; Massimo Poncino; Enrico Macii (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A Portable 3-D Imaging FMCW MIMO Radar Demonstrator With a $24 times 24$ Antenna Array for Medium-Range Applications. - Alexander Rudolf Ganis; Enric Miralles Navarro; Bernhard Schoenlinner; Ulrich Prechtel; Askold Meusling; Christoph Heller; Thomas Spreng; Jan Mietzner; Christian Krimmer; Babette Haeberle; Steffen Lutz; Mirko Loghi; et al. (IEEE Trans. Geosci. Remote. Sens., 2018)

Modelling and design of FTJs as high reading-impedance synaptic devices. - Riccardo Fontanini; Marco Massarotto; Ruben Specogna; Francesco Driussi; Mirko Loghi; David Esseni (CoRR, 2021)

Ferroelectric based FETs and synaptic devices for highly energy efficient computational technologies. - David Esseni; Riccardo Fontanini; Daniel Lizzit; Marco Massarotto; Francesco Driussi; Mirko Loghi (CoRR, 2021)

Reducing the Spike Rate in Deep Spiking Neural Networks. - Riccardo Fontanini; David Esseni; Mirko Loghi (ICONS, 2022)

Adiabatic Spiking Neurons and Synapses for Ultra-Low Energy Neuromorphic Computing. - Marco Massarotto; Stefano Saggini; Mirko Loghi; David Esseni (ICECS, 2023)

Reducing the spike rate of deep spiking neural networks based on time-encoding. - Riccardo Fontanini; Alessandro Pilotto; David Esseni; Mirko Loghi (Neuromorph. Comput. Eng., 2024)