ChiBench: a Benchmark Suite for Testing Electronic Design Automation Tools. - Rafael Sumitani; João Victor Amorim; Augusto Mafra; Mirlaine Crepalde; Fernando Magno Quintão Pereira (CoRR, 2024)

Automatic Test Case Generation for Jasper App HDL Compiler: An Industry Experience. - Mirlaine Crepalde; Augusto Mafra; Lucas Cavalini; Lucas Martins; Guilherme Amorim; Pedro Henrique Santos; Fabiano Peixoto (CC, 2025)

Bottom-Up Generation of Verilog Designs for Testing EDA Tools. - João Victor Amorim; Luiza de Melo Gomes; Rafael Sumitani; Raissa Maciel; Augusto Mafra; Mirlaine Crepalde; Fernando Magno Quintão Pereira (CoRR, 2025)