Concurrent fault simulation and functional level modeling. - Miron Abramovici; Melvin A. Breuer; K. Kumar (DAC, 1977)

On Redundancy and Fault Detection in Sequential Circuits. - Miron Abramovici; Melvin A. Breuer (IEEE Trans. Computers, 1979)

Fault diagnosis based on effect-cause analysis: An introduction. - Miron Abramovici; Melvin A. Breuer (DAC, 1980)

Multiple Fault Diagnosis in Combinational Circuits Based on an Effect-Cause Analysis. - Miron Abramovici; Melvin A. Breuer (IEEE Trans. Computers, 1980)

A maximal resolution guided-probe testing algorithm. - Miron Abramovici (DAC, 1981)

A Hierarchical, Path-Oriented Approach to Fault Diagnosis in Modular Combinational Circuits. - Miron Abramovici (IEEE Trans. Computers, 1982)

Fault Diagnosis in Synchronous Sequential Circuits Based on an Effect-Cause Analysis. - Miron Abramovici; Melvin A. Breuer (IEEE Trans. Computers, 1982)

A Logic Simulation Machine. - Miron Abramovici; Ytzhak H. Levendel; Premachandran R. Menon (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983)

Critical Path Tracing: An Alternative to Fault Simulation. - Miron Abramovici; Prem R. Menon; David T. Miller (IEEE Des. Test, 1984)

Low-Cost Fault Simulation: Why, When and How. - Miron Abramovici (ITC, 1985)

Test Generation In Lamp2: System Overview. - Miron Abramovici; James J. Kulikowski; Premachandran R. Menon; David T. Miller (ITC, 1985)

Test Generation In Lamp2: Concepts and Algorithms. - Miron Abramovici; James J. Kulikowski; Premachandran R. Menon; David T. Miller (ITC, 1985)

A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. - Miron Abramovici; Prem R. Menon (IEEE Trans. Computers, 1985)

SMART and FAST: Test Generation for VLSI Scan-Design Circuits. - Miron Abramovici; James J. Kulikowski; Premachandran R. Menon; David T. Miller (IEEE Des. Test, 1986)

Checkpoint Faults are not Sufficient Target Faults for Test Generation. - Miron Abramovici; Prem R. Menon; David T. Miller (IEEE Trans. Computers, 1986)

Critical path tracing in sequential circuits. - Prem R. Menon; Ytzhak H. Levendel; Miron Abramovici (ICCAD, 1988)

What is the Path to Fast Fault Simulation? - Miron Abramovici; Balaji Krishnamurthy; Rob Mathews; Bill Rogers; Michael Schulz; Sharad Seth; John A. Waicukauski (ITC, 1988)

System-level design verification in the AT&T computer division: overview and strategy. - Miron Abramovici; J. W. Bierbauer; R. H. Hellman; C. L. Hong; David T. Miller; R. G. Taylor (ICCD, 1989)

System-level design verification in the AT&T Computer Division: tools. - Miron Abramovici; James J. Kulikowski; David T. Miller; Prem R. Menon (ICCD, 1989)

Digital systems testing and testable design. - Miron Abramovici; Melvin A. Breuer; Arthur D. Friedman (Computer Science Press, 1990)

Global cost functions for test generation. - Miron Abramovici; David T. Miller; R. Henning (ITC, 1990)

The Best Flip-Flops to Scan. - Miron Abramovici; James J. Kulikowski; Rabindra K. Roy (ITC, 1991)

SCRIPT: a critical path tracing algorithm for synchronous sequential circuits. - Premachandran R. Menon; Ytzhak H. Levendel; Miron Abramovici (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Freeze!: A New Approach for Testing Sequential Circuits. - Miron Abramovici; Krishna B. Rajan; David T. Miller (DAC, 1992)

One-Pass Redundancy Identification and Removal. - Miron Abramovici; Mahesh A. Iyer (ITC, 1992)

Warning: 100% Fault Coverage May Be Misleading!! - Miron Abramovici; Prashant S. Parikh (ITC, 1992)

Dynamic redundancy identification in automatic test generation. - Miron Abramovici; David T. Miller; Rabindra K. Roy (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992)

A Cost-Based Approach to Partial Scan. - Prashant S. Parikh; Miron Abramovici (DAC, 1993)

DOs and DON'Ts in Computing Fault Coverage. - Miron Abramovici (ITC, 1993)

On Selecting Flip-Flops for Partial Reset. - Miron Abramovici; Prashant S. Parikh; Ben Mathew; Daniel G. Saab (ITC, 1993)

Sequentially Untestable Faults Identified Without Search ("Simple Implications Beat Exhaustive Search!"). - Mahesh A. Iyer; Miron Abramovici (ITC, 1994)

Low-Cost Redundancy Identification for Combinatorial Circuits. - Mahesh A. Iyer; Miron Abramovici (VLSI Design, 1994)

On Combining Design for Testability Techniques. - Prashant S. Parikh; Miron Abramovici (ITC, 1995)

Identifying sequentially untestable faults using illegal states. - David E. Long; Mahesh A. Iyer; Miron Abramovici (VTS, 1995)

Testability-based partial scan analysis. - Prashant S. Parikh; Miron Abramovici (J. Electron. Test., 1995)

Identifying Sequential Redundancies Without Search. - Mahesh A. Iyer; David E. Long; Miron Abramovici (DAC, 1996)

Surprises in Sequential Redundancy Identification. - Mahesh A. Iyer; David E. Long; Miron Abramovici (ED&TC, 1996)

Evaluation of FPGA Resources for Built-In Self-Test of Programmable Logic Blocks. - Charles E. Stroud; Ping Chen; Srinivasa Konala; Miron Abramovici (FPGA, 1996)

Using ILA Testing for BIST in FPGAs. - Charles E. Stroud; Eric Lee; Srinivasa Konala; Miron Abramovici (ITC, 1996)

Increasing testability by clock transformation (getting rid of those darn states). - Krishna B. Rajan; David E. Long; Miron Abramovici (VTS, 1996)

Built-in self-test of logic blocks in FPGAs (Finally, a free lunch: BIST without overhead!). - Charles E. Stroud; Srinivasa Konala; Ping Chen; Miron Abramovici (VTS, 1996)

FIRE: a fault-independent combinational redundancy identification algorithm. - Mahesh A. Iyer; Miron Abramovici (IEEE Trans. Very Large Scale Integr. Syst., 1996)

Fault simulation on reconfigurable hardware. - Miron Abramovici; Prem R. Menon (FCCM, 1997)

Satisfiability on reconfigurable hardware. - Miron Abramovici; Daniel G. Saab (FPL, 1997)

BIST-Based Diagnostics of FPGA Logic Blocks. - Charles E. Stroud; Eric Lee; Miron Abramovici (ITC, 1997)

Built-in self-test of FPGA interconnect. - Charles E. Stroud; Sajitha Wijesuriya; Carter Hamilton; Miron Abramovici (ITC, 1998)

A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware. - Miron Abramovici; José T. de Sousa; Daniel G. Saab (DAC, 1999)

FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy. - Yanti Santoso; Matthew C. Merten; Elizabeth M. Rudnick; Miron Abramovici (DATE, 1999)

A Virtual Logic Algorithm for Solving Satisfiability Problems Using Reconfigurable Hardware. - Miron Abramovici; José T. de Sousa (FCCM, 1999)

Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications. - Miron Abramovici; Charles E. Stroud; Carter Hamilton; Sajitha Wijesuriya; Vinay Verma (ITC, 1999)

Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration. - John Marty Emmert; Charles E. Stroud; Brandon Skaggs; Miron Abramovici (FCCM, 2000)

Performance Penalty for Fault Tolerance in Roving STARs. - John Marty Emmert; Charles E. Stroud; Jason A. Cheatham; Andrew M. Taylor; Pankaj Kataria; Miron Abramovici (FPL, 2000)

Improving On-Line BIST-Based Diagnosis for Roving STARs. - Miron Abramovici; Charles E. Stroud; Brandon Skaggs; John Marty Emmert (IOLTW, 2000)

DIST-based detection and diagnosis of multiple faults in FPGAs. - Miron Abramovici; Charles E. Stroud (ITC, 2000)

MUST: multiple-stem analysis for identifying sequentially untestable faults. - Qiang Peng; Miron Abramovici; Jacob Savir (ITC, 2000)

A SAT Solver Using Reconfigurable Hardware and Virtual Logic. - Miron Abramovici; José T. de Sousa (J. Autom. Reason., 2000)

Compact Test Generation Using a Frozen Clock Testing Strategy. - Elizabeth M. Rudnick; Miron Abramovici (J. Inf. Sci. Eng., 2000)

FILL and FUNI: algorithms to identify illegal states and sequentially untestable faults. - David E. Long; Mahesh A. Iyer; Miron Abramovici (ACM Trans. Design Autom. Electr. Syst., 2000)

On-Line Fault Tolerance for FPGA Interconnect with Roving STARs. - John Marty Emmert; Stanley Baumgart; Pankaj Kataria; Andrew M. Taylor; Charles E. Stroud; Miron Abramovici (DFT, 2001)

Roving Stars: An Integrated Approach To On-Line Testing, Diagnosis, And Fault Tolerance For Fpgas In Adaptive Computing Systems. - Miron Abramovici; John Marty Emmert; Charles E. Stroud (Evolvable Hardware, 2001)

A Configurable Hardware/Software Approach to SAT Solving. - José T. de Sousa; J. M. da Silva; Miron Abramovici (FCCM, 2001)

On-Line BIST and Diagnosis of FPGA Interconnect Using Roving STARs. - Miron Abramovici; Charles E. Stroud; Matthew Lashinsky; Jeremy Nall; John Marty Emmert (IOLTW, 2001)

At-speed logic BIST using a frozen clock testing strategy. - Jongshin Shin; Xiaoming Yu; Elizabeth M. Rudnick; Miron Abramovici (ITC, 2001)

Design for Testability Techniques: A Comparative Analysis. - Miron Abramovici (LATW, 2001)

Sequential ATPG Using Combinational Algorithms. - Miron Abramovici; Xiaoming Yu; Elizabeth M. Rudnick (LATW, 2001)

BIST-based test and diagnosis of FPGA logic blocks. - Miron Abramovici; Charles E. Stroud (IEEE Trans. Very Large Scale Integr. Syst., 2001)

Using embedded FPGAs for SoC yield improvement. - Miron Abramovici; Charles E. Stroud; John Marty Emmert (DAC, 2002)

Low-cost sequential ATPG with clock-control DFT. - Miron Abramovici; Xiaoming Yu; Elizabeth M. Rudnick (DAC, 2002)

BIST-Based Diagnosis of FPGA Interconnect. - Charles E. Stroud; Jeremy Nall; Matthew Lashinsky; Miron Abramovici (ITC, 2002)

BIST-Based Delay-Fault Testing in FPGAs. - Miron Abramovici; Charles E. Stroud (J. Electron. Test., 2003)

Online BIST and BIST-based diagnosis of FPGA logic blocks. - Miron Abramovici; Charles E. Stroud; John Marty Emmert (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Sequential circuit ATPG using combinational algorithms. - Xiaoming Yu; Miron Abramovici (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A reconfigurable design-for-debug infrastructure for SoCs. - Miron Abramovici; Paul Bradley; Kumar N. Dwarakanath; Peter Levin; Gérard Memmi; Dave Miller (DAC, 2006)

Online Fault Tolerance for FPGA Logic Blocks. - John Marty Emmert; Charles E. Stroud; Miron Abramovici (IEEE Trans. Very Large Scale Integr. Syst., 2007)

You can catch more bugs with transaction level honey. - Miron Abramovici; Kees Goossens; Bart Vermeulen; Jack Greenbaum; Neal Stollon; Adam Donlin (CODES+ISSS, 2008)

In-system silicon validation using a reconfigurable platform. - Miron Abramovici (HLDVT, 2008)

In-System Silicon Validation and Debug. - Miron Abramovici (IEEE Des. Test Comput., 2008)

Integrated circuit security: new threats and solutions. - Miron Abramovici; Paul Bradley (CSIIRW, 2009)

We need more standards like IEEE 1500. - Miron Abramovici; Al Crouch (IEEE Des. Test Comput., 2009)

Bridging pre-silicon verification and post-silicon validation. - Amir Nahir; Avi Ziv; Rajesh Galivanche; Alan J. Hu; Miron Abramovici; Albert Camilleri; Bob Bentley; Harry Foster; Valeria Bertacco; Shakti Kapoor (DAC, 2010)

Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution. - Swarup Bhunia; Miron Abramovici; Dakshi Agrawal; Paul Bradley; Michael S. Hsiao; Jim Plusquellic; Mohammad Tehranipoor (IEEE Des. Test, 2013)

Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test. - Sandeep Gupta 001; Miron Abramovici; Magdy Abadir; Sridhar Narayanan (VTS, 2017)