A 27S/32S DC-balanced line coding scheme for PAM-4 signaling. - Miryala Chandra Shekar; Sandeep Goyal; Shalabh Gupta (VLSID, 2021)

A 0.009mm2, 0-230mA Wide-range Load Current Output Capacitor-less Low Dropout Regulator for High Bandwidth Memory parallel IOs. - Javed S. Gaggatur; Miryala Chandra Shekar; Komal Deshmukh (VLSID, 2022)

A 0.5pJ/bit 7.2Gbps HBM3 PHY on Intel4 with EMIB Packaging and Unmatched Receiver Architecture on PHY Side with Per Bit Deskew Correction. - Aakash Hasmukhray Mehta; Javed S. Gaggatur; Mohammad M. Rashid; Sampath Dakshinamurthy; Aruna Kumar Lakya Srinivasamurthy; Anil Kumar Goyal; Subbarao Manam; Harshit Gupta; Sandeep Sukumar; Vipin K. Mishra; Koushik N. S; Santosh Nekkanti; et al. (VLSID, 2025)