Programming in a mother tongue: philosophy, implementation, practice and effect. - Toshio Souya; Eiichi Hayakawa; Masayuki Honma; Hidehiro Fukushima; Mitaro Namiki; Nobumasa Takahashi; Masaki Nakagawa (COMPSAC, 1991)

Performance Evaluation of an On-Chip Multi-Threaded Processor with Cache Memory Managed by Logical Thread Number. - Hironori Nakajo; Masanori Yamato; Shoji Kawahara; Norito Kato; Koichi Sasada; Mikiko Sato; Mitaro Namiki (PDPTA, 2003)

Implementation and Evaluation of a Thread Library for Multithreaded Architecture. - Koichi Sasada; Mikiko Sato; Shoji Kawahara; Norito Kato; Masanori Yamato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2003)

A Process and Thread Management of the Operating System "Future" for On Chip Multithreaded Architecture. - Mikiko Sato; Koichi Sasada; Shoji Kawahara; Norito Kato; Masanori Yamato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2003)

Dynamic Allocation of Physical Register Banks for an SMT Processor. - Norito Kato; Masanori Yamato; Osamu Tujimoto; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Mitaro Namiki; Hironori Nakajo (PDPTA, 2004)

A New Model of Reconfigurable Cache for an SMT Processor and its FPGA Implementation. - Yoshiyasu Ogasawara; Norito Kato; Masanori Yamato; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Mitaro Namiki; Hironori Nakajo (PDPTA, 2005)

Development of a Thread Scheduler for SMT Processor Architecture. - Kaname Uchikura; Koichi Sasada; Mikiko Sato; Masanori Yamato; Norito Kato; Hironori Nakajo; Mitaro Namiki (PDPTA, 2005)

Implementation of PC Cluster System with Memory Mapped File by Commodity OS. - Jun Kanai; Takuro Mori; Takeshi Araki; Noboru Tanabe; Hironori Nakajo; Mitaro Namiki (PDPTA, 2006)

Towards Reconfigurable Cache Memory for a Multithreaded Processor. - Yoshiyasu Ogasawara; Ippei Tate; Satoshi Watanabe; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)

A Model of Implementable SMT Processor on FPGA. - Ippei Tate; Yoshiyasu Ogasawara; Mikiko Sato; Koichi Sasada; Kaname Uchikura; Kazunari Asano; Satoshi Watanabe; Mitaro Namiki; Hironori Nakajo (PDPTA, 2006)

Mobile Thin-Client System with Fault Tolerance and Scalability by "HTTP-FUSE-KNOPPIX-BOX". - Jun Kanai; Mitaro Namiki; Kuniyasu Suzaki; Toshiki Yagi (PDPTA, 2007)

A fine-grain dynamic sleep control scheme in MIPS R3000. - Naomi Seki; Lei Zhao; Jo Kei; Daisuke Ikebuchi; Yu Kojima; Yohei Hasegawa; Hideharu Amano; Toshihiro Kashima; Seidai Takeda; Toshiaki Shirai; Mitsutaka Nakata; Kimiyoshi Usami; et al. (ICCD, 2008)

Green Multicore-SoC Software-Execution Framework with Timely-Power-Gating Scheme. - Masafumi Onouchi; Keisuke Toyama 003; Tohru Nojiri; Makoto Sato; Masayoshi Mase; Jun Shirako; Mikiko Sato; Masashi Takada; Masayuki Ito; Hiroyuki Mizuno; Mitaro Namiki; Keiji Kimura; et al. (ICPP, 2009)

A CS unplugged design pattern. - Tomohiro Nishida; Susumu Kanemune; Yukio Idosaka; Mitaro Namiki; Tim Bell 001; Yasushi Kuno (SIGCSE, 2009)

Design and Implementation of Fine-Grain Power Gating with Ground Bounce Suppression. - Kimiyoshi Usami; Toshiaki Shirai; Tatsunori Hashida; Hiroki Masuda; Seidai Takeda; Mitsutaka Nakata; Naomi Seki; Hideharu Amano; Mitaro Namiki; Masashi Imai; Masaaki Kondo; Hiroshi Nakamura (VLSI Design, 2009)

Geyser-1: a MIPS R3000 CPU core with fine-grained run-time power gating. - Daisuke Ikebuchi; Naomi Seki; Yu Kojima; M. Kamata; Lei Zhao; Hideharu Amano; Toshiaki Shirai; Satoshi Koyama; Tatsunori Hashida; Y. Umahashi; Hiroki Masuda; Kimiyoshi Usami; et al. (ASP-DAC, 2010)

Proposal of a multi-core processor from the viewpoint of evolutionary computation. - Mikiko Sato; Yuji Sato; Mitaro Namiki (IEEE Congress on Evolutionary Computation, 2010)

Proposal of a multi-core processor architecture for effective evolutionary computation. - Mikiko Sato; Yuji Sato; Mitaro Namiki (GECCO, 2010)

Reducing instruction TLB's leakage power consumption for embedded processors. - Zhao Lei; Hui Xu; Daisuke Ikebuchi; Hideharu Amano; Tetsuya Sunata; Mitaro Namiki (Green Computing Conference, 2010)

Adaptive power gating for function units in a microprocessor. - Kimiyoshi Usami; Tatsunori Hashida; Satoshi Koyama; Tatsuya Yamamoto; Daisuke Ikebuchi; Hideharu Amano; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ISQED, 2010)

Geyser-2: The second prototype CPU with fine-grained run-time power gating. - Lei Zhao; Daisuke Ikebuchi; Yoshiki Saito; M. Kamata; Naomi Seki; Yu Kojima; Hideharu Amano; Satoshi Koyama; Tatsunori Hashida; Y. Umahashi; D. Masuda; Kimiyoshi Usami; et al. (ASP-DAC, 2011)

SLD-1(Silent Large Datapath): A ultra low power reconfigurable accelerator. - Nobuaki Ozaki; Kimiyoshi Usami; Hideharu Amano; Mitaro Namiki; Hiroshi Nakamura; Masaaki Kondo (COOL Chips, 2011)

Cool Mega-Array: A highly energy efficient reconfigurable accelerator. - Nobuaki Ozaki; Yoshihiro Yasuda; Yoshiki Saito; Daisuke Ikebuchi; Masayuki Kimura; Hideharu Amano; Hiroshi Nakamura; Kimiyoshi Usami; Mitaro Namiki; Masaaki Kondo (FPT, 2011)

Acceleration experiment of genetic computations for sudoku solution on multi-core processors. - Mikiko Sato; Yuji Sato; Mitaro Namiki (GECCO (Companion), 2011)

CS Unplugged Assisted by Digital Materials for Handicapped People at Schools. - Hiroki Manabe; Susumu Kanemune; Mitaro Namiki; Yoshiaki Nakano (ISSEP, 2011)

A Leakage Efficient Instruction TLB Design for Embedded Processors. - Zhao Lei; Hui Xu; Daisuke Ikebuchi; Tetsuya Sunata; Mitaro Namiki; Hideharu Amano (IEICE Trans. Inf. Syst., 2011)

A Leakage Efficient Data TLB Design for Embedded Processors. - Lei Zhao; Hui Xu; Daisuke Ikebuchi; Tetsuya Sunata; Mitaro Namiki; Hideharu Amano (IEICE Trans. Inf. Syst., 2011)

Design and Implementation Fine-grained Power Gating on Microprocessor Functional Units. - Zhao Lei; Daisuke Ikebuchi; Kimiyoshi Usami; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura; Hideharu Amano (IPSJ Trans. Syst. LSI Des. Methodol., 2011)

Cool Mega-Arrays: Ultralow-Power Reconfigurable Accelerator Chips. - Nobuaki Ozaki; Yoshihiro Yasuda; Mai Izawa; Yoshiki Saito; Daisuke Ikebuchi; Hideharu Amano; Hiroshi Nakamura; Kimiyoshi Usami; Mitaro Namiki; Masaaki Kondo (IEEE Micro, 2011)

CMA-Cube: A scalable reconfigurable accelerator with 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Eiichi Sasaki; Hideharu Amano; Hiroki Matsutani; Yasuhiro Take; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2012)

Dynamic power control with a heterogeneous multi-core system using a 3-D wireless inductive coupling interconnect. - Yusuke Koizumi; Hideharu Amano; Hiroki Matsutani; Noriyuki Miura; Tadahiro Kuroda; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPT, 2012)

A design of hybrid operating system for a parallel computer with multi-core and many-core processors. - Mikiko Sato; Go Fukazawa; Kiyohiko Nagamine; Ryuichi Sakamoto; Mitaro Namiki; Kazumi Yoshinaga; Yuichi Tsujita; Atsushi Hori; Yutaka Ishikawa (ROSS@ICS, 2012)

An Efficient Kernel-Level Blocking MPI Implementation. - Atsushi Hori; Toyohisa Kameyama; Yuichi Tsujita; Mitaro Namiki; Yutaka Ishikawa (EuroMPI, 2012)

Delegation-Based MPI Communications for a Hybrid Parallel Computer with Many-Core Architecture. - Kazumi Yoshinaga; Yuichi Tsujita; Atsushi Hori; Mikiko Sato; Mitaro Namiki; Yutaka Ishikawa (EuroMPI, 2012)

An OpenCL Runtime Library for Embedded Multi-Core Accelerator. - Ryuichi Sakamoto; Mikiko Sato; Yusuke Koizumi; Hideharu Amano; Mitaro Namiki (RTCSA, 2012)

Geyser. - Hiroshi Sasaki 001; Hideharu Amano; Kimiyoshi Usami; Masaaki Kondo; Mitaro Namiki; Hiroshi Nakamura (Handbook of Energy-Aware and Green Computing, 2012)

Hardware support for resource partitioning in real-time embedded systems. - Tetsuro Honmura; Yuki Kondo; Tetsuya Yamada; Masashi Takada; Takumi Nitoh; Tohru Nojiri; Keisuke Toyama 003; Yasuhiko Saitoh; Hirofumi Nishi; Mikiko Sato; Mitaro Namiki (COOL Chips, 2013)

Demonstration of a heterogeneous multi-core processor with 3-D inductive coupling links. - Yusuke Koizumi; Noriyuki Miura; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (FPL, 2013)

A scalable 3D heterogeneous multi-core processor with inductive-coupling thruchip interface. - Noriyuki Miura; Yusuke Koizumi; Eiichi Sasaki; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (Hot Chips Symposium, 2013)

sQoS: The design and prototyping of secure QoS for process automation system. - Hiroshi Miyata; Mitaro Namiki; Mikiko Sato (IECON, 2013)

A Delegation Mechanism on Many-Core Oriented Hybrid Parallel Computers for Scalability of Communicators and Communications in MPI. - Kazumi Yoshinaga; Yuichi Tsujita; Atsushi Hori; Mikiko Sato; Mitaro Namiki; Yutaka Ishikawa (PDP, 2013)

Improving Parallel I/O Performance Using Multithreaded Two-Phase I/O with Processor Affinity Management. - Yuichi Tsujita; Kazumi Yoshinaga; Atsushi Hori; Mikiko Sato; Mitaro Namiki; Yutaka Ishikawa (PPAM (1), 2013)

Fine-Grained Run-Tume Power Gating through Co-optimization of Circuit, Architecture, and System Software Design. - Hiroshi Nakamura; Weihan Wang; Yuya Ohta; Kimiyoshi Usami; Hideharu Amano; Masaaki Kondo; Mitaro Namiki (IEICE Trans. Electron., 2013)

A Scalable 3D Heterogeneous Multicore with an Inductive ThruChip Interface. - Noriyuki Miura; Yusuke Koizumi; Yasuhiro Take; Hiroki Matsutani; Tadahiro Kuroda; Hideharu Amano; Ryuichi Sakamoto; Mitaro Namiki; Kimiyoshi Usami; Masaaki Kondo; Hiroshi Nakamura (IEEE Micro, 2013)

Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessors. - Kimiyoshi Usami; Masaru Kudo; Kensaku Matsunaga; Tsubasa Kosaka; Yoshihiro Tsurui; Weihan Wang; Hideharu Amano; Hiroaki Kobayashi; Ryuichi Sakamoto; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ASP-DAC, 2014)

A fine grained power management supported by just-in-time compiler. - Motoki Wada; Mikiko Sato; Mitaro Namiki (COOL Chips, 2014)

Design and evaluation of fine-grained power-gating for embedded microprocessors. - Masaaki Kondo; Hiroaki Kobayashi; Ryuichi Sakamoto; Motoki Wada; Jun Tsukamoto; Mitaro Namiki; Weihan Wang; Hideharu Amano; Kensaku Matsunaga; Masaru Kudo; Kimiyoshi Usami; Toshiya Komoda; et al. (DATE, 2014)

First results of performance comparisons on many-core processors in solving QAP with ACO: kepler GPU versus xeon PHI. - Mikiko Sato; Shigeyoshi Tsutsui; Noriyuki Fujimoto; Yuji Sato; Mitaro Namiki (GECCO (Companion), 2014)

pmqFlow: Design of propagation time measuring QoS system with OpenFlow for process automation. - Hiroshi Miyata; Mitaro Namiki; Mikiko Sato (IECON, 2014)

Unbalanced buffer tree synthesis to suppress ground bounce for fine-grain power gating. - Kimiyoshi Usami; Makoto Miyauchi; Masaru Kudo; Kazumitsu Takagi; Hideharu Amano; Mitaro Namiki; Masaaki Kondo; Hiroshi Nakamura (ISSoC, 2014)

Multithreaded Two-Phase I/O: Improving Collective MPI-IO Performance on a Lustre File System. - Yuichi Tsujita; Kazumi Yoshinaga; Atsushi Hori; Mikiko Sato; Mitaro Namiki; Yutaka Ishikawa (PDP, 2014)

Design of Multiple PVAS on InfiniBand Cluster System Consisting of Many-core and Multi-core. - Mikiko Sato; Go Fukazawa; Akio Shimada; Atsushi Hori; Yutaka Ishikawa; Mitaro Namiki (EuroMPI/ASIA, 2014)

A Fine-Grained Power Gating Control on Linux Monitoring Power Consumption of Processor Functional Units. - Atsushi Koshiba; Motoki Wada; Ryuichi Sakamoto; Mikiko Sato; Tsubasa Kosaka; Kimiyoshi Usami; Hideharu Amano; Masaaki Kondo; Hiroshi Nakamura; Mitaro Namiki (IEICE Trans. Electron., 2015)

An Operating System Guided Fine-Grained Power Gating Control Based on Runtime Characteristics of Applications. - Atsushi Koshiba; Mikiko Sato; Kimiyoshi Usami; Hideharu Amano; Ryuichi Sakamoto; Masaaki Kondo; Hiroshi Nakamura; Mitaro Namiki (IEICE Trans. Electron., 2016)

Building block multi-chip systems using inductive coupling through chip interface. - Hideharu Amano; Tadahiro Kuroda; Hiroshi Nakamura; Kimiyoshi Usami; Masaaki Kondo; Hiroki Matsutani; Mitaro Namiki (ISOCC, 2017)

Building block operating system for 3D stacked computer systems with inductive coupling interconnect. - Shinsuke Hamada; Atsushi Koshiba; Mitaro Namiki; Hideharu Amano (ISOCC, 2017)

Towards write-back aware software emulator for non-volatile memory. - Atsushi Koshiba; Takahiro Hirofuchi; Soramichi Akiyama; Ryousei Takano; Mitaro Namiki (NVMSA, 2017)

TEE-KV: Secure Immutable Key-Value Store for Trusted Execution Environments. - Atsushi Koshiba; Ying Yan; Zhongxin Guo; Mitaro Namiki; Lidong Zhou (SoCC, 2018)

Design and development of bit arrow: a web-based programming learning environment. - Kazuhei Nagashima; Shinya Cho; Masayuki Horikoshi; Hiroki Manabe; Susumu Kanemune; Mitaro Namiki (ICETC, 2018)

End-to-End Delay Model for Remote Surveillance over Internet and Mobile Networks. - May Takada; Mitaro Namiki (ISPACS, 2018)

OpenCL Runtime for OS-Driven Task Pipelining on Heterogeneous Accelerators. - Atsushi Koshiba; Ryuichi Sakamoto; Mitaro Namiki (RTCSA, 2018)

Reactive NaN Repair for Applying Approximate Memory to Numerical Applications. - Shinsuke Hamada; Soramichi Akiyama; Mitaro Namiki (CoRR, 2018)

A Preliminary Evaluation of Building Block Computing Systems. - Sayaka Terashima; Takuya Kojima; Hayate Okuhara; Kazusa Musha; Hideharu Amano; Ryuichi Sakamoto; Masaaki Kondo; Mitaro Namiki (MCSoC, 2019)

A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies. - Atsushi Koshiba; Takahiro Hirofuchi; Ryousei Takano; Mitaro Namiki (IEICE Trans. Inf. Syst., 2019)

M-KUBOS/PYNQ Cluster for multi-access edge computing. - Takumi Inage; Kazuei Hironaka; Kensuke Iizuka; Kohei Ito; Yasuyu Fukushima; Mitaro Namiki; Hideharu Amano (CANDAR, 2021)