A Two-Level Reconfigurable Architecture for Digital Signal Processing. - Mitchell J. Myjak; José G. Delgado-Frias (VLSI, 2003)

H-Tree Interconnection Structure for Reconfigurable DSP Hardware. - Mitchell J. Myjak; Fredrick L. Anderson; José G. Delgado-Frias (ERSA, 2004)

Pipelined Multipliers for Reconfigurable Hardware. - Mitchell J. Myjak; José G. Delgado-Frias (IPDPS, 2004)

Enhanced Fault-Tolerant Data Latches for Deep Submicron CMOS. - Daniel R. Blum; Mitchell J. Myjak; José G. Delgado-Frias (CDES, 2005)

A Symmetric Differential Clock Generator for Bit-Serial Hardware. - Mitchell J. Myjak; José G. Delgado-Frias (CDES, 2005)

Mapping and Performance of DSP Benchmarks on a Medium-Grain Reconfigurable Architecture. - Mitchell J. Myjak; Jonathan Larson; José G. Delgado-Frias (ERSA, 2006)

Superpipelined reconfigurable hardware for DSP. - Mitchell J. Myjak; José G. Delgado-Frias (ISCAS, 2006)

Medium-Grain Cells for Reconfigurable DSP Hardware. - Mitchell J. Myjak; José G. Delgado-Frias (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance. - Mitchell J. Myjak; José G. Delgado-Frias (IEEE Trans. Very Large Scale Integr. Syst., 2008)

A Frequency-Programmable Miniaturized Radio Frequency Transmitter for Animal Tracking. - Jun Lu; Huidong Li; Chuan Tian; Mitchell J. Myjak; Jie Xiao; Brian J. Bellgraph; Samuel S. Cartmell; Zhiqun Daniel Deng (Sensors, 2021)