A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. - Subho Chatterjee; Mitchelle Rasquinha; Sudhakar Yalamanchili; Saibal Mukhopadhyay (ICCAD, 2009)

An energy efficient cache design using spin torque transfer (STT) RAM. - Mitchelle Rasquinha; Dhruv Choudhary; Subho Chatterjee; Saibal Mukhopadhyay; Sudhakar Yalamanchili (ISLPED, 2010)

Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments. - Syed Minhaj Hassan; Dhruv Choudhary; Mitchelle Rasquinha; Sudhakar Yalamanchili (PACT, 2011)

A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. - Subho Chatterjee; Mitchelle Rasquinha; Sudhakar Yalamanchili; Saibal Mukhopadhyay (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Manifold: A parallel simulation framework for multicore systems. - Jun Wang 077; Jesse G. Beu; Rishiraj A. Bheda; Tom Conte 001; Zhenjiang Dong; Chad D. Kersey; Mitchelle Rasquinha; George F. Riley; William J. Song; He Xiao; Peng Xu; Sudhakar Yalamanchili (ISPASS, 2014)

A Metric Driven Approach to Mixed Precision Training. - Mitchelle Rasquinha; Gil Tabak (CoRR, 2024)