A Feed-Forward Time-Multiplexed Neural Network with Mixed-Signal Neuron-Synapse Arrays. - Mitra Mirhassani; Majid Ahmadi; William C. Miller (VLSI, 2003)

A new mixed-signal feed-forward neural network with on-chip learning. - Mitra Mirhassani; Majid Ahmadi; William C. Miller (IJCNN, 2004)

Digital Multiplication using Continuous Valued Digits. - Mitra Mirhassani; Majid Ahmadi; Graham A. Jullien (ISCAS, 2007)

Robust analog neural network based on continuous valued number system. - Mitra Mirhassani; Majid Ahmadi; Graham A. Jullien (ISCAS, 2008)

Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing. - Mitra Mirhassani; Majid Ahmadi; Graham A. Jullien (IEEE Trans. Very Large Scale Integr. Syst., 2008)

An area-speed efficient method for current mode analog to digital converters. - Golnar Khodabndehloo; Mitra Mirhassani; Majid Ahmadi (ECCTD, 2009)

Mixed-signal CVNS adder for two-operand binary addition. - Mitra Mirhassani (EIT, 2009)

Current-mode Multiple-valued Dynamic Memory. - Golnar Khodabndehloo; Mitra Mirhassani; Majid Ahmadi (ISCAS, 2009)

16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin. - Golnar Khodabndehloo; Mitra Mirhassani; Majid Ahmadi (ISMVL, 2009)

System-level design of low complexity CVNS feed forward neural network. - Mitra Mirhassani; Babak Zamanlooy (ISCAS, 2010)

Resistive-Type CVNS Distributed Neural Networks With Improved Noise-to-Signal Ratio. - Golnar Khodabandehloo; Mitra Mirhassani; Majid Ahmadi (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

A study on resistive-type truncated CVNS Distributed Neural Networks. - Golnar Khodabandehloo; Mitra Mirhassani; Majid Ahmadi (ISCAS, 2011)

Error Recovery in Continuous Valued Number System. - Mitra Mirhassani; Majid Ahmadi; Graham A. Jullien (J. Circuits Syst. Comput., 2011)

CVNS-Based Storage and Refreshing Scheme for a Multi-Valued Dynamic Memory. - Golnar Khodabandehloo; Mitra Mirhassani; Majid Ahmadi (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Current mode multiple-valued adder for cryptography processors. - Ashley Novak; Farinoush Saffar; Mitra Mirhassani; Huapeng Wu (ISCAS, 2012)

A Fault-Tolerant Area-Efficient Current-Mode ADC for Multiple-Valued Neural Networks. - Farinoush Saffar; Mitra Mirhassani; Majid Ahmadi (ISMVL, 2012)

Complexity Study of the Continuous Valued Number System Adders. - Babak Zamanlooy; Ashley Novak; Mitra Mirhassani (ISMVL, 2012)

Efficient hardware implementation of threshold neural networks. - Babak Zamanlooy; Mitra Mirhassani (NEWCAS, 2012)

A Prototype CVNS Distributed Neural Network Using Synapse-Neuron Modules. - Golnar Khodabandehloo; Mitra Mirhassani; Majid Ahmadi (IEEE Trans. Circuits Syst. I Regul. Pap., 2012)

Analog Implementation of a Novel Resistive-Type Sigmoidal Neuron. - Golnar Khodabandehloo; Mitra Mirhassani; Majid Ahmadi (IEEE Trans. Very Large Scale Integr. Syst., 2012)

A low cost biomimetic implementation of a CPG based on AdEx neuron model. - Shaghayegh Gomar; Arash Ahmadi; Shahpour Alirezaee; Majid Ahmadi; Mitra Mirhassani (ICECS, 2014)

Area efficient low-sensitivity lumped madaline based on Continuous Valued Number System. - Babak Zamanlooy; Mitra Mirhassani (ISCAS, 2014)

A temperature compensated relaxation oscillator for SoC implementations. - Iman Y. Taha; Mitra Mirhassani (NEWCAS, 2014)

Area-efficient robust Madaline based on continuous valued number system. - Babak Zamanlooy; Mitra Mirhassani (Neurocomputing, 2014)

Efficient VLSI Implementation of Neural Networks With Hyperbolic Tangent Activation Function. - Babak Zamanlooy; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A modular mixed-signal CVNS neural network architecture. - Farinoush Saffar; Mitra Mirhassani; Majid Ahmadi (IJCNN, 2015)

CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning. - Babak Zamanlooy; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Precise digital implementations of hyperbolic tanh and sigmoid function. - Shaghayegh Gomar; Mitra Mirhassani; Majid Ahmadi (ACSSC, 2016)

A digital neuromorphic circuit for neural-glial interaction. - Shaghayegh Gomar; Mitra Mirhassani; Majid Ahmadi; Mehrdad Saif (IJCNN, 2016)

A 24GHz Digitally Controlled Oscillator for automotive radar in 65nm CMOS. - Iman Y. Taha; Mitra Mirhassani (ISCAS, 2016)

Analog cellular neural network for application in physical unclonable functions. - Hadis Takaloo; Arash Ahmadi; Mitra Mirhassani; Majid Ahmadi (ISCAS, 2016)

Efficient mixed-signal synapse multipliers for multi-layer feed-forward neural networks. - Bahar Youssefi; Mitra Mirhassani; Q. M. Jonathan Wu (MWSCAS, 2016)

Two-electrode ECG measurement circuit using a feed forward CMRR enhancement method. - Esrafil Jedari; Rashid Rashidzadeh; Mitra Mirhassani; Majid Ahmadi (CCECE, 2017)

An efficient FPGA implementation of Optical Character Recognition for License Plate Recognition. - Yuan Jing; Bahar Youssefi; Mitra Mirhassani; Roberto Muscedere (CCECE, 2017)

A software tool for generating optimized multipartite table parameters. - Roberto Muscedere; Mitra Mirhassani (CCECE, 2017)

A CMOS differential DCO with amplitude stabilization for 24GHz automotive radars. - Iman Y. Taha; Mitra Mirhassani (CCECE, 2017)

A neural network architecture using high resolution multiplying digital to analog converters. - Farinoush Saffar; Mitra Mirhassani; Majid Ahmadi (MWSCAS, 2017)

Positive feedback technique and split-length transistors for DC-gain enhancement of two-stage op-amps. - Seyed Mahmoud Anisheh; Hossein Shamsi; Mitra Mirhassani (IET Circuits Devices Syst., 2017)

Mixed-signal VLSI neural network based on Continuous Valued Number System. - Babak Zamanlooy; Mitra Mirhassani (Neurocomputing, 2017)

An Analog CVNS-Based Sigmoid Neuron for Precise Neurochips. - Babak Zamanlooy; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Hardware Realization of Mixed-Signal Neural Networks with Modular Synapse-Neuron arrays. - Bahar Youssefi; Alexander J. Leigh; Mitra Mirhassani; Q. M. Jonathan Wu (ISCAS, 2018)

A Monotonically Linear DCO for 77 GHz Automotive Radars. - Iman Y. Taha; Mitra Mirhassani; Arezoo Emadi (MWSCAS, 2018)

Review of Arithmetic Operations Using the Continuous Valued Number System. - Babak Zamanlooy; Mitra Mirhassani; Majid Ahmadi (MWSCAS, 2018)

A Varactor-Less DCO With 7GHz Tuning Range for 77GHz Automotive Radars. - Iman Y. Taha; Mitra Mirhassani (IEEE Access, 2019)

Tunable Neuron With PWL Approximation Based on the Minimum Operator. - Bahar Youssefi; Alexander J. Leigh; Mitra Mirhassani; Q. M. Jonathan Wu (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 24-GHz DCO With High-Amplitude Stabilization and Enhanced Startup Time for Automotive Radar. - Iman Y. Taha; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2019)

An Efficient Spiking Neuron Hardware System Based on the Hardware-Oriented Modified Izhikevich Neuron (HOMIN) Model. - Alexander J. Leigh; Mitra Mirhassani; Roberto Muscedere (IEEE Trans. Circuits Syst., 2020)

Ultra low-power negative DC voltage generator based on a proposed level shifter and voltage reference. - Neda Rezaei; Mitra Mirhassani (Microelectron. J., 2021)

An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation. - Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF. - Madhan Thirumoorthi; Marko Jovanovic; Mitra Mirhassani; Mohammed A. S. Khalid (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Selective Input Sparsity in Spiking Neural Networks for Pattern Classification. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (ISCAS, 2022)

A Low-Resource Digital Implementation of the Fitzhugh-Nagumo Neuron. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (PRIME, 2022)

A High-Accuracy Digital Implementation of the Morris-Lecar Neuron With Variable Physiological Parameters. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Corrections to "An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FPGA Implementation". - Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A Pre-Activation, Golden IC Free, Hardware Trojan Detection Approach. - Hamidreza Esmaeili Taheri; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An Optimized M-Term Karatsuba-Like Binary Polynomial Multiplier for Finite Field Arithmetic. - Madhan Thirumoorthi; Moslem Heidarpur; Mitra Mirhassani; Mohammed A. S. Khalid (IEEE Trans. Very Large Scale Integr. Syst., 2022)

High-Performance FPGA Implementation of Fully Connected Networks of SAM Neurons. - Edris Zaman Farsa; Moslem Heidarpur; Arash Ahmadi; Mitra Mirhassani (ISCAS, 2023)

Digital Hardware Implementations of Spiking Neural Networks With Selective Input Sparsity for Edge Inferences in Controlled Image Acquisition Environments. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A Resource-Efficient and High-Accuracy CORDIC-Based Digital Implementation of the Hodgkin-Huxley Neuron. - Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Novel Formulations of M-Term Overlap-Free Karatsuba Binary Polynomial Multipliers and Their Hardware Implementations. - Madhan Thirumoorthi; Alexander J. Leigh; Moslem Heidarpur; Mohammed A. S. Khalid; Mitra Mirhassani (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Developing a fuzzy optimized model for selecting a maintenance strategy in the paper industry: An integrated FGP-ANP-FMEA approach. - Foroogh Behnia; Habib Zare Ahmadabadi; Beth-Anne Schuelke Leech; Mitra Mirhassani (Expert Syst. Appl., 2023)

Cyber Resiliency Enhancement of Overcurrent Relays in Distribution Systems. - Saad Pola; Marko Jovanovic; Maher A. Azzouz; Mitra Mirhassani (IEEE Trans. Smart Grid, 2024)

A High Speed and Area Efficient Processor for Elliptic Curve Scalar Point Multiplication for GF(2m). - Madhan Thirumoorthi; Alexander J. Leigh; Moslem Heidarpur; Mitra Mirhassani; Mohammed A. S. Khalid (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Novel and Efficient Large Integer Number Theoretic Transform Multiplier Based on Unified Blocks. - Shiva Nejati 002; Moslem Heidarpur; Mitra Mirhassani (LASCAS, 2025)

Toward Full GPU Acceleration of Agile Homomorphic Encryption Frameworks. - Emilio Quaggiotto; Shiva Nejati 002; Alexander J. Leigh; Mitra Mirhassani (LASCAS, 2025)

System Engineering-Based Threat Modeling for Heavy-Duty Vehicles. - Narges Rahimi; Beth-Anne Schuelke Leech; Mitra Mirhassani (SysCon, 2025)

A comprehensive review of security vulnerabilities in heavy-duty vehicles: Comparative insights and current research gaps. - Narges Rahimi; Beth-Anne Schuelke Leech; Mitra Mirhassani (Comput. Secur., 2025)

Enhanced TARA model for heavy-duty vehicles using ISO/SAE 21434 and Fuzzy Analytic Hierarchy Process (FAHP). - Narges Rahimi; Beth-Anne Schuelke Leech; Mitra Mirhassani (Expert Syst. Appl., 2025)

A Fully Pipelined FIFO Based Polynomial Multiplication Hardware Architecture Based On Number Theoretic Transform. - Moslem Heidarpur; Mitra Mirhassani; Norman Chang (CoRR, 2025)