Buffer assignment for data driven architectures. - Dhiraj K. Pradhan; Mitrajit Chatterjee; Savita Banerjee (ICCAD, 1993)

LOT: logic optimization with testability-new transformations using recursive learning. - Mitrajit Chatterjee; Dhiraj K. Pradhan; Wolfgang Kunz (ICCAD, 1995)

A novel pattern generator for near-perfect fault-coverage. - Mitrajit Chatterjee; Dhiraj K. Pradhan (VTS, 1995)

BIT-based weighted mean filter. - Barun K. Kar; Mitrajit Chatterjee; Dhiraj K. Pradhan (EUSIPCO, 1996)

Gate-level synthesis for low-power using new transformations. - Dhiraj K. Pradhan; Mitrajit Chatterjee; Madhu V. Swarna; Wolfgang Kunz (ISLPED, 1996)

LOT: Logic Optimization with Testability. New transformations for logic synthesis. - Mitrajit Chatterjee; Dhiraj K. Pradhan; Wolfgang Kunz (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998)

GLFSR-a new test pattern generator for built-in-self-test. - Dhiraj K. Pradhan; Mitrajit Chatterjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

Buffer Assignment Algorithms on Data Driven ASICs. - Mitrajit Chatterjee; Savita Banerjee; Dhiraj K. Pradhan (IEEE Trans. Computers, 2000)

VERILAT: verification using logic augmentation and transformations. - Debjyoti Paul; Mitrajit Chatterjee; Dhiraj K. Pradhan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000)

A BIST Pattern Generator Design for Near-Perfect Fault Coverage. - Mitrajit Chatterjee; Dhiraj K. Pradhan (IEEE Trans. Computers, 2003)