Bitline GND sensing technique for low-voltage operation FeRAM. - Shoichiro Kawashima; Toru Endo; Akira Yamamoto; Ken-ichi Nakabayashi; Mitsuharu Nakazawa; Keizo Morita; Masaki Aoki (IEEE J. Solid State Circuits, 2002)

A Reliable 1T1C FeRAM Using a Thermal History Tracking 2T2C Dual Reference Level Technique for a Smart Card Application Chip. - Shoichiro Kawashima; Isao Fukushi; Keizo Morita; Ken-ichi Nakabayashi; Mitsuharu Nakazawa; Kazuaki Yamane; Tomohisa Hirayama; Toru Endo (IEICE Trans. Electron., 2007)

An 8-Mbit 0.18-µm CMOS 1T1C FeRAM in Planar Technology. - Shoichiro Kawashima; Keizo Morita; Mitsuharu Nakazawa; Kazuaki Yamane; Mitsuhiro Ogai; Kuninori Kawabata; Kazuaki Takai; Yasuhiro Fujii; Ryoji Yasuda; Wensheng Wang; Yukinobu Hikosaka; Ken'ichi Inoue (IEICE Trans. Electron., 2015)