A New Timing Calibration Method for High Speed Memory Test. - Yasumasa Nishimura; Mitsuhiro Hamada; Y. Hayasaka (ITC, 1984)

Redundancy Test for 1 Mbit DRAM Using Multi-Bit-Test Mode. - Yasumasa Nishimura; Mitsuhiro Hamada; Hideto Hidaka; Hideyuki Ozaki; Kazuyasu Fujishima; Y. Hayasaka (ITC, 1986)

A redundancy test-time reduction technique in 1-Mbit DRAM with a multibit test mode. - Yasumasa Nishimura; Mitsuhiro Hamada; Hideto Hidaka; Hideyuki Ozaki; Kazuyasu Fujishima (IEEE J. Solid State Circuits, 1989)

A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM. - Narumi Sakashita; Fumihiro Okuda; Ken'ichi Shimomura; Hiroki Shimano; Mitsuhiro Hamada; Tetsuo Tada; Shinji Komori; Kazuo Kyuma; Akihiko Yasuoka; Haruhiko Abe (ITC, 1996)

A built-in self-repair analyzer (CRESTA) for embedded DRAMs. - Tomoya Kawagoe; Jun Ohtani; Mitsutaka Niiro; Tukasa Ooishi; Mitsuhiro Hamada; Hideto Hidaka (ITC, 2000)