Vulnerability of a communication network with a satellite. - Kenichi Hagihara; Toshimitsu Masuzawa; Nobuki Tokura; Mitsuji Ikeda (Syst. Comput. Jpn., 1985)

Enhanced Delay Test Generator for High-Speed Logic LSIs. - Kazumi Hatayama; Mitsuji Ikeda; Terumine Hayashi; Masahiro Takakura; Kuniaki Kishida; Shun Ishiyama (ITC, 1989)

Sequential Test Generation Based on Real-Value Logic. - Kazumi Hatayama; Kazunori Hikone; Mitsuji Ikeda; Terumine Hayashi (ITC, 1992)

Sequential circuit test generation by real number simulation. - Kazunori Hikone; Mitsuji Ikeda; Kazumi Hatayama; Terumine Hayashi (Syst. Comput. Jpn., 1993)

Application of a Design for Delay Testability Approach to High Speed Logic LSIs. - Kazumi Hatayama; Mitsuji Ikeda; Masahiro Takakura; Satoshi Uchiyama; Yoriyuki Sakamoto (Asian Test Symposium, 1997)