A 9-M tr. access network system-on-a-chip for mega-bit Internet access at home. - Shinichi Kozu; Toshiya Aramaki; Chinatsu Ikeda; Yasuaki Kuroda; Satoru Kawanago; Mitsuji Okada; Hiroshi Kariya; Masao Manabe; Hirotaka Utani; Eiji Sudou; Yukihiro Oda; Hideo Suzukii (CICC, 2000)

A 2.1-to-2.8GHz all-digital frequency synthesizer with a time-windowed TDC. - Takashi Tokairin; Mitsuji Okada; Masaki Kitsunezuka; Tadashi Maeda; Muneo Fukaishi (ISSCC, 2010)

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter. - Takashi Tokairin; Mitsuji Okada; Masaki Kitsunezuka; Tadashi Maeda; Muneo Fukaishi (IEEE J. Solid State Circuits, 2010)

A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique. - Shunichi Kaeriyama; Shinichi Uchida; Masayuki Furumiya; Mitsuji Okada; Tadashi Maeda; Masayuki Mizuno (IEEE J. Solid State Circuits, 2012)

A 24-transistor static flip-flop consisting of nors and inverters for low-power digital vlsis. - Yuzuru Shizuku; Tetsuya Hirose; Nobutaka Kuroki; Masahiro Numa; Mitsuji Okada (NEWCAS, 2014)

Energy-efficient AES SubBytes transformation circuit using asynchronous circuits for ultra-low voltage operation. - Yuzuru Shizuku; Tetsuya Hirose; Nobutaka Kuroki; Masahiro Numa; Mitsuji Okada (IEICE Electron. Express, 2015)

An Energy-Efficient 24T Flip-Flop Consisting of Standard CMOS Gates for Ultra-Low Power Digital VLSIs. - Yuzuru Shizuku; Tetsuya Hirose; Nobutaka Kuroki; Masahiro Numa; Mitsuji Okada (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

Live Demonstration: A Non-Contact Transmission Line Connector for USB3.1 HD-Video Streaming. - Tomoya Arakawa; Joshin Sone; Mitsuji Okada; Mototsugu Hamada; Tadahiro Kuroda (ISCAS, 2019)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM with an Inductive Coupling Interface Using Over-SRAM Coils and Manchester-Encoded Synchronous Transceivers. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (HCS, 2022)

Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (NEWCAS, 2022)

A 7-nm FinFET 1.2-TB/s/mm2 3D-Stacked SRAM Module With 0.7-pJ/b Inductive Coupling Interface Using Over-SRAM Coil and Manchester-Encoded Synchronous Transceiver. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE J. Solid State Circuits, 2023)

Polyomino: A 3D-SRAM-Centric Accelerator for Randomly Pruned Matrix Multiplication With Simple Reordering Algorithm and Efficient Compression Format in 180-nm CMOS. - Kota Shiba; Mitsuji Okada; Atsutake Kosuge; Mototsugu Hamada; Tadahiro Kuroda (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)