Design of 4-kbit*4-layer optically coupled three-dimensional common memory for parallel processor system. - Mitsumasa Koyanagi; Hidehiro Takata; Hiroki Mori; Junichiro Iba (IEEE J. Solid State Circuits, 1990)

A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections. - Mitsumasa Koyanagi (VLSI, 1991)

A New Multiport Memory for High Performance Parallel Processor System with Shared Memory. - Keiichi Hirano; Taizou Ono; Hiroyuki Kurino; Mitsumasa Koyanagi (ASP-DAC, 1998)

Future system-on-silicon LSI chips. - Mitsumasa Koyanagi; Hiroyuki Kurino; Kang Wook Lee 002; Katsuyuki Sakuma; Nobuaki Miyakawa; Hikotaro Itani (IEEE Micro, 1998)

Smart Vision Chip Fabricated Using Three Dimensional Integration Technology. - Hiroyuki Kurino; Masaki Nakagawa; Kang Wook Lee 002; Tomonori Nakamura; Yuusuke Yamada; Ki Tae Park; Mitsumasa Koyanagi (NIPS, 2000)

Nanometer design: what hurts next...? - Robert W. Brodersen; Anthony M. Hill; John Kibarian; Desmond Kirkpatrick; Mark A. Lavin; Mitsumasa Koyanagi (DAC, 2002)

Parallel image processing field programmable gate array for real time image processing system. - Takeaki Sugimura; JeoungChill Shim; Hiroyuki Kurino; Mitsumasa Koyanagi (FPT, 2003)

Design of A Novel Real-Shared Memory Module for High Performance Parallel Processor System with Shared Memory. - Zhe Liu 005; JeoungChill Shim; Hiroyuki Kurino; Mitsumasa Koyanagi (AINA (2), 2004)

Design and Evaluation of a Novel Real-Shared Cache Module for High Performance Parallel Processor Chip. - Zhe Liu 005; JeoungChill Shim; Hiroyuki Kurino; Mitsumasa Koyanagi (PDCAT, 2004)

Dynamic Multi-Context Reconfiguration Scheme for Reconfigurable Parallel Image Processing System with Three Dimensional Structure. - Takeaki Sugimura; Yuta Konishi; Yoshihiro Nakatani; Takafumi Fukushima; Hiroyuki Kurino; Mitsumasa Koyanagi (ARCS Workshops, 2005)

Development of a High Speed Vision System for Mobile Robots. - Atsushi Konno; Ryo Uchikura; Toshiyuki Ishihara; Teppei Tsujita; Takeaki Sugimura; Jun Deguchi; Mitsumasa Koyanagi; Masaru Uchiyama (IROS, 2006)

Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. - Ji Chel Bea; Mariappan Murugesan; Yuki Ohara; Akihiro Noriki; Hisashi Kino; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch. - Takafumi Fukushima; Eiji Iwata; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

3D integration technology for 3D stacked retinal chip. - Yoshiyuki Kaiho; Yuki Ohara; Hirotaka Takeshita; Kouji Kiyoyama; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

A parallel ADC for high-speed CMOS image processing system with 3D structure. - Kouji Kiyoyama; Yuki Ohara; Kang Wook Lee 002; Y. Yang; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

Heterogeneous integration technology for MEMS-LSI multi-chip module. - Kang Wook Lee 002; Shigeyuki Kanno; Yuki Ohara; Kouji Kiyoyama; Ji Chel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. - Yuki Ohara; Akihiro Noriki; Katsuyuki Sakuma; Kang Wook Lee 002; Mariappan Murugesan; Jichoel Bea; Fumiaki Yamada; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2009)

Three-dimensional integration technology and integrated systems. - Mitsumasa Koyanagi; Takafumi Fukushima; Tetsu Tanaka (ASP-DAC, 2009)

High-Density Through Silicon Vias for 3-D LSIs. - Mitsumasa Koyanagi; Takafumi Fukushima; Tetsu Tanaka (Proc. IEEE, 2009)

Evaluation of alignment accuracy on chip-to-wafer self-assembly and mechanism on the direct chip bonding at room temperature. - Takafumi Fukushima; Eiji Iwata; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

A block-parallel signal processing system for CMOS image sensor with three-dimensional structure. - Kouji Kiyoyama; Kang Wook Lee 002; Takafumi Fukushima; H. Naganuma; Hiroaki Kobayashi; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Impact of microbump induced stress in thinned 3D-LSIs after wafer bonding. - Mariappan Murugesan; Yuki Ohara; Jichoel Bea; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Through Silicon photonic via (TSPV) with Si core for low loss and high-speed data transmission in opto-electronic 3-D LSI. - Akihiro Noriki; Kang Wook Lee 002; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

Three-dimensional integration technology using through-si via based on reconfigured wafer-to-wafer bonding. - Mitsumasa Koyanagi; Takafumi Fukushima; Tetsu Tanaka (CICC, 2010)

Temporary bonding strength control for self-assembly-based 3D integration. - Takafumi Fukushima; Yuki Ohara; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Chip-level TSV integration for rapid prototyping of 3D system LSIs. - Kazuyuki Hozawa; Futoshi Furuta; Yuko Hanaoka; Mayu Aoki; Kenichi Takeda; Katsuyuki Sakuma; Kang Wook Lee 002; Takafumi Fukushima; Mitsumasa Koyanagi (3DIC, 2011)

High-bandwidth data transmission of new transceiver module through optical interconnection. - Yuka Ito; Shinsuke Terada; Shinya Arai; Koji Choki; Takafumi Fukushima; Mitsumasa Koyanagi (3DIC, 2011)

A very low area ADC for 3-D stacked CMOS image processing system. - Kouji Kiyoyama; Kang Wook Lee 002; Takafumi Fukushima; H. Naganuma; H. Kobayashi; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

High reliable and fine size of 5-μm diameter backside Cu through-silicon Via(TSV) for high reliability and high-end 3-D LSIs. - Kang Wook Lee 002; Jichoel Bea; Takafumi Fukushima; Yuki Ohara; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Stacked SOI pixel detector using versatile fine pitch μ-bump technology. - Makoto Motoyoshi; Junichi Takanohashi; Takafumi Fukushima; Yasuo Arai; Mitsumasa Koyanagi (3DIC, 2011)

W/Cu TSVs for 3D-LSI with minimum thermo-mechanical stress. - Mariappan Murugesan; Hideto Hashiguchi; Harufumi Kobayashi; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

High density Cu-TSVs and reliability issues. - Mariappan Murugesan; Harufumi Kobayashi; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Fabrication tolerance evaluation of high efficient unidirectional optical coupler for though silicon photonic via in optoelectronic 3D-LSI. - Akihiro Noriki; Kang Wook Lee 002; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

Novel detachable bonding process with wettability control of bonding surface for versatile chip-level 3D integration. - Yuki Ohara; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

3D super chip technology to achieve low-power and high-performance system-on-a chip. - Mitsumasa Koyanagi (ISLPED, 2011)

Self-Assembly of Chip-Size Components with Cavity Structures: High-Precision Alignment and Direct Bonding without Thermal Compression for Hetero Integration. - Takafumi Fukushima; Takayuki Konno; Eiji Iwata; Risato Kobayashi; Toshiya Kojima; Mariappan Murugesan; Ji Chel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (Micromachines, 2011)

A 19nm 112.8mm2 64Gb multi-level flash memory with 400Mb/s/pin 1.8V Toggle Mode interface. - Noboru Shibata; Kazushige Kanda; Toshiki Hisada; Katsuaki Isobe; Manabu Sato; Yui Shimizu; Takahiro Shimizu; Takahiro Sugimoto; Tomohiro Kobayashi; Kazuko Inuzuka; Naoaki Kanagawa; Yasuyuki Kajitani; et al. (ISSCC, 2012)

Development of via-last 3D integration technologies using a new temporary adhesive system. - Takafumi Fukushima; Jichoel Bea; Mariappan Murugesan; Kang Wook Lee 002; Mitsumasa Koyanagi (3DIC, 2013)

3D memory chip stacking by multi-layer self-assembly technology. - Takafumi Fukushima; Jichoel Bea; Mariappan Murugesan; Ho-Young Son; Min-Suk Suh; K.-Y. Byun; N.-S. Kim; Kang Wook Lee 002; Mitsumasa Koyanagi (3DIC, 2013)

Highly efficient TSV repair technology for resilient 3-D stacked multicore processor system. - Hiroyuki Hashimoto; Takafumi Fukushima; Kang Wook Lee 002; Mitsumasa Koyanagi; Tetsu Tanaka (3DIC, 2013)

A block-parallel ADC with digital noise cancelling for 3-D stacked CMOS image sensor. - Kouji Kiyoyama; Y. Sato; Hiroyuki Hashimoto; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2013)

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. - Kang Wook Lee 002; Seiya Tanikawa; Mariappan Murugesan; H. Naganuma; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2013)

Effect of CVD Mn oxide layer as Cu diffusion barrier for TSV. - Mariappan Murugesan; Jichoel Bea; Kang Wook Lee 002; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi; Yuji Sutou; H. Wang; J. Koike (3DIC, 2013)

Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration. - Takafumi Fukushima; Yuka Ito; Mariappan Murugesan; Jicheol Bea; Kang Wook Lee 002; Koji Choki; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2014)

Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV. - K. W. Lee; Chisato Nagai; Ai Nakamura; Ji Chel Bea; Mariappan Murugesan; Takafumi Fukushima; Tanaka Tanaka; Mitsumasa Koyanagi (3DIC, 2014)

Transfer and non-transfer stacking technologies based on chip-to-wafer self-asembly for high-throughput and high-precision alignment and microbump bonding. - Takafumi Fukushima; Taku Suzuki; Hideto Hashiguchi; Chisato Nagai; Jichoel Bea; Hiroyuki Hashimoto; Mariappan Murugesan; Kang Wook Lee 002; Tetsu Tanaka; Kazushi Asami; Yasuhiro Kitamura; Mitsumasa Koyanagi (3DIC, 2015)

Consideration of microbump layout for reduction of local bending stress due to CTE Mismatch in 3D IC. - Hisashi Kino; Hideto Hashiguchi; Seiya Tanikawa; Yohei Sugawara; Shunsuke Ikegaya; Takafumi Fukushima; Mitsumasa Koyanagi; Tetsu Tanaka (3DIC, 2015)

Reconfigured multichip-on-wafer (mCoW) Cu/oxide hybrid bonding technology for ultra-high density 3D integration using recessed oxide, thin glue adhesive, and thin metal capping layers. - K. W. Lee; Chisato Nagai; Ai Nakamura; Hiroki Aizawa; Ji Chel Bea; Mitsumasa Koyanagi; Hideto Hashiguchi; Takafumi Fukushima; Tanaka Tanaka (3DIC, 2015)

Novel local stress evaluation method in 3D IC using DRAM cell array with planar mOS capacitors. - Seiya Tanikawa; Hisashi Kino; Takafumi Fukushima; Mitsumasa Koyanagi; Tetsu Tanaka (3DIC, 2015)

Vacuum-assisted-spin-coating of polyimide liner for high-aspect-ratio TSVs applications. - Yangyang Yan; Yingtao Ding; Qianwen Chen; Kang Wook Lee 002; Takafumi Fukushima; Mitsumasa Koyanagi (3DIC, 2015)

Impacts of 3-D integration processes on device reliabilities in thinned DRAM chip for 3-D DRAM. - Kang Wook Lee 002; Ji Chel Bea; Mariappan Murugesan; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (IRPS, 2015)

Recent progress in 3D integration technology. - Mitsumasa Koyanagi (IEICE Electron. Express, 2015)

New concept of TSV formation methodology using Directed Self-Assembly (DSA). - Takafumi Fukushima; Mariappan Murugesan; Shin Ohsaki; Hiroyuki Hashimoto; Jichoel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2016)

Nano-scale Cu direct bonding using ultra-high density Cu nano-pillar (CNP) for high yield exascale 2.5/3D integration applications. - Kang Wook Lee 002; Ai Nakamura; Jicheol Bea; Takafumi Fukushima; Suresh Ramalingam; Xin Wu; Tanaka Tanaka; Mitsumasa Koyanagi (3DIC, 2016)

3 Dimensional stacked pixel detector and sensor technology using less than 3-μmφ robust bump junctions. - Makoto Motoyoshi; Kohki Yanagimura; Taikoh Fushimi; Junichi Takanohashi; Mariappan Murugesan; Masahiro Aoyagi; Mitsumasa Koyanagi (3DIC, 2016)

Improving the integrity of Ti barrier layer in Cu-TSVs through self-formed TiSix for via-last TSV technology. - Mariappan Murugesan; Jichel Bea; Takafumi Fukushima; Makoto Motoyoshi; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2016)

Oxide-Oxide Thermocompression Direct Bonding Technologies with Capillary Self-Assembly for Multichip-to-Wafer Heterogeneous 3D System Integration. - Takafumi Fukushima; Hideto Hashiguchi; Hiroshi Yonekura; Hisashi Kino; Mariappan Murugesan; Ji Chel Bea; Kang Wook Lee 002; Tetsu Tanaka; Mitsumasa Koyanagi (Micromachines, 2016)

Cu-Cu Bonding Challenges with 'i-ACF' for Advanced 3D Integration. - Shunji Kurooka; Yoshinori Hotta; Ai Nakamura; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2019)

Growth Optimization of Multi-Layer Graphene for Thermal-TSV Application in 3D-LSI. - Mariappan Murugesan; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2019)

Fabrication and Morphological Characterization of Nano-Scale Interconnects for 3D-Integration. - Mariappan Murugesan; Mitsumasa Koyanagi; Hiroyuki Hashimoto; Ji Chel Bea; Takafumi Fukushima (3DIC, 2019)

3D Heterogeneous Integration Technology for AI System. - Mitsumasa Koyanagi (VLSI-DAT, 2020)

Integration of Damage-less Probe Cards Using Nano-TSV Technology for Microbumped Wafer Testing. - Takafumi Fukushima; Shinichi Sakuyama; Masatomo Takahashi; Hiroyuki Hashimoto; Jichoel Bea; Theodorus Marcello; Hisashi Kino; Tetsu Tanaka; Mitsumasa Koyanagi; Mariappan Murugesan (3DIC, 2021)

Implementation of a Chaotic Neural Network Reservoir on a TSV/μBump Stacked 3D Cyclic Neural Network Integrated Circuit. - Yoshihiko Horio; Takemori Orima; Koji Kiyoyama; Mitsumasa Koyanagi (3DIC, 2021)

Design for 3-D Stacked Neural Network Circuit with Cyclic Analog Computing. - Koji Kiyoyama; Yoshihiko Horio; Takafumi Fukushima; Hiroyuki Hashimoto; Takemori Orima; Mitsumasa Koyanagi (3DIC, 2021)

Cu-Cu Direct Bonding Through Highly Oriented Cu Grains for 3D-LSI Applications. - Mariappan Murugesan; E. Sone; A. Simomura; Makoto Motoyoshi; Masahiro Sawa; K. Fukuda; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2021)

Copper Electrode Surface Features and Cu-SiO2Hybrid Bonding. - Mariappan Murugesan; Masahiro Sawa; E. Sone; Makoto Motoyoshi; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2023)

Impact of Super-long-throw PVD on TSV Metallization and Die-to-Wafer 3D Integration Based on Via-last. - Jiayi Shen; Chang Liu; Tadaaki Hoshi; Atsushi Shinoda; Hisashi Kino; Tetsu Tanaka; Mariappan Murugesan; Mitsumasa Koyanagi; Takafumi Fukushima (3DIC, 2023)