Special parallel processor for lu decomposition of a large-scale sparse matrix. - Hideki Asai; Mitsuo Asai; Mamoru Tanaka (Syst. Comput. Jpn., 1987)

Design, fabrication and evaluation of a 5-inch wafer scale neural network LSI composed on 576 digital neurons. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Minoru Yamada; Akira Masaki (IJCNN, 1990)

The SDC cell-A novel design methodology for high-speed arithmetic modules using CMOS/BiCMOS precharged circuits. - Takehisa Hayashi; Toshio Doi; Mitsuo Asai; Kenichi Ishibashi; Shoji Shukuri; Atsuo Watanabe; Makoto Suzuki (IEEE J. Solid State Circuits, 1990)

A self-learning digital neural network using wafer-scale LSI. - Moritoshi Yasunaga; Noboru Masuda; Masayoshi Yagyu; Mitsuo Asai; Katsunari Shibata; Mitsuo Ooyama; Minoru Yamada; Takahiro Sakaguchi; Masashi Hashimoto (IEEE J. Solid State Circuits, 1993)

A PA-RISC Mikroprocessor PA/50L For Low-Cost Systems. - Tetsuhiko Okada; Susumu Narita; Osamu Nishii; Noriharu Hiratsuka; Nobuyuki Hayashi; Mitsuo Asai; Shinji Fujiwara; Mikiko Satoh; Junichi Nishimoto; Hirokazu Aoki; Kunio Uchiyama; Shigeru Matsuo; et al. (COMPCON, 1994)