Design method for an over-IO-Gb/s CMOS CML buffer circuit for delay control. - Keiji Kishine; Hiromi Inaba; Yusuke Ohtomo; Makoto Nakamura; Mitsuo Nakamura (MWSCAS, 2012)

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS. - Keiji Kishine; Hiromi Inaba; Yusuke Ohtomo; Makoto Nakamura; Hiroshi Koizumi; Mitsuo Nakamura (MWSCAS, 2013)

A 280-MHz CMOS Intra-Symbol Intermittent RF Front End for Adaptive Power Reduction of Wireless Receivers According to Received-Signal Intensity in Sensor Networks. - Mitsuo Nakamura; Mamoru Ugajin; Mitsuru Harada (IEICE Trans. Electron., 2013)

An On-The-Fly Jitter Suppression Technique for Plain-CMOS-Logic-Based Timing Verniers: Dynamic Power Compensation with the Extensions of Digitally Variable Delay Lines. - Nobutaro Shibata; Mitsuo Nakamura (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018)