A Noise-Coupled Time-Interleaved ΔΣ ADC with 4.2MHz BW, -98dB THD, and 79dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (ISSCC, 2008)

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR. - Kyehyung Lee; Jeongseok Chae; Mitsuru Aniya; Koichi Hamashita; Kaoru Takasuka; Seiji Takeuchi; Gabor C. Temes (IEEE J. Solid State Circuits, 2008)

A 63 dB 16 mW 20 MHz BW double-sampled ΔΣs analog-to-digital converter with an embedded-adder quantizer. - Jeongseok Chae; Sanghyeon Lee; Mitsuru Aniya; Seiji Takeuchi; Koichi Hamashita; Pavan Kumar Hanumolu; Gabor C. Temes (CICC, 2010)

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC. - Omid Rajaee; Tawfiq Musah; Nima Maghari; Seiji Takeuchi; Mitsuru Aniya; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2010)

A double-sampled low-distortion cascade ΔΣ modulator with an adder/integrator for WLAN application. - Sanghyeon Lee; Jeongseok Chae; Mitsuru Aniya; Seiji Takeuchi; Koichi Hamashita; Pavan Kumar Hanumolu; Gabor C. Temes (CICC, 2011)

Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer. - Omid Rajaee; Seiji Takeuchi; Mitsuru Aniya; Koichi Hamashita; Un-Ku Moon (IEEE J. Solid State Circuits, 2011)

A 19.2-mW, 81.6-dB SNDR, 4-MHz bandwidth delta-sigma modulator with shifted loop delays. - Xin Meng; Jinzhou Cao; Tao He 001; Yi Zhang 023; Gabor C. Temes; Mitsuru Aniya; Kazuki Sobue; Koichi Hamashita (ESSCIRC, 2015)