Optimized redundancy selection based on failure-related yield model for 64-Mb DRAM and beyond. - Shigeru Kikuda; Hiroshi Miyamoto; Shigeru Mori; Mitsutaka Niiro; Michihiro Yamada (IEEE J. Solid State Circuits, 1991)

A built-in self-repair analyzer (CRESTA) for embedded DRAMs. - Tomoya Kawagoe; Jun Ohtani; Mitsutaka Niiro; Tukasa Ooishi; Mitsuhiro Hamada; Hideto Hidaka (ITC, 2000)

A shared built-in self-repair analysis for multiple embedded memories. - Jun Ohtani; Tukasa Ooishi; Tomoya Kawagoe; Mitsutaka Niiro; Masanao Maruta; Hideto Hidaka (CICC, 2001)

A 1.0-V 230-MHz column access embedded DRAM for portable MPEG applications. - Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Masatoshi Ishikawa; Toshihiro Inokuchi; Hiroshi Kato; Hiroaki Tanizaki; Wataru Abe; Akinori Shibayama; Yoshifumi Fukushima; Mitsutaka Niiro; Masanao Maruta; et al. (IEEE J. Solid State Circuits, 2001)

A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test. - Shigeki Tomishima; Hiroaki Tanizaki; Mitsutaka Niiro; Masanao Maruta; Hideto Hidaka; T. Tada; Kenji Gamo (ITC, 2002)

0.13-μm 32-Mb/64-Mb embedded DRAM core with high efficient redundancy and enhanced testability. - Hirohito Kikukawa; Shigeki Tomishima; Takaharu Tsuji; Toshiaki Kawasaki; Shouji Sakamoto; Masatoshi Ishikawa; Wataru Abe; Hiroaki Tanizaki; Hiroshi Kato; Toshitaka Uchikoba; Toshihiro Inokuchi; Manabu Senoh; et al. (IEEE J. Solid State Circuits, 2002)

A 312-MHz 16-Mb random-cycle embedded DRAM macro with a power-down data retention mode for mobile applications. - Fukashi Morishita; Isamu Hayashi; Hideto Matsuoka; Kazuhiro Takahashi; Kuniyasu Shigeta; Takayuki Gyohten; Mitsutaka Niiro; Hideyuki Noda; Mako Okamoto; Atsushi Hachisuka; Atsushi Amo; Hiroki Shinkawata; et al. (IEEE J. Solid State Circuits, 2005)