Substrate-noise and random-fluctuations reduction with self-adjusted forward body bias. - Yoshihide Komatsu; Koichiro Ishibashi; Masaharu Yamamoto; Toshiro Tsukada; Kenji Shimazaki; Mitsuya Fukazawa; Makoto Nagata (CICC, 2005)

An integrated timing and dynamic supply noise verification for nano-meter CMOS SoC designs. - Kenji Shimazaki; Mitsuya Fukazawa; Makoto Nagata; Shingo Miyahara; Masaaki Hirata; Kazuhiro Satoh; Hiroyuki Tsujikawa (CICC, 2005)

A built-in power supply noise probe for digital LSIs. - Mitsuya Fukazawa; Koichiro Noguchi; Makoto Nagata; Kazuo Taki (ASP-DAC, 2006)

Delay Variation Analysis in Consideration of Dynamic Power Supply Noise Waveform. - Mitsuya Fukazawa; Makoto Nagata (CICC, 2006)

Measurement-Based Analysis of Delay Variation Induced by Dynamic Power Supply Noise. - Mitsuya Fukazawa; Makoto Nagata (IEICE Trans. Electron., 2006)

An Integrated Timing and Dynamic Supply Noise Verification for Multi-10-Million Gate SoC Designs. - Kenji Shimazaki; Makoto Nagata; Mitsuya Fukazawa; Shingo Miyahara; Masaaki Hirata; Kazuhiro Satoh; Hiroyuki Tsujikawa (IEICE Trans. Electron., 2006)

Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. - Mitsuya Fukazawa; Tetsuro Matsuno; Toshifumi Uemura; Rei Akiyama; Tetsuya Kagemoto; Hiroshi Makino; Hidehiro Takata; Makoto Nagata (ISSCC, 2007)

Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations. - Mitsuya Fukazawa; Masanori Kurimoto; Rei Akiyama; Hidehiro Takata; Makoto Nagata (IEICE Trans. Electron., 2009)

A High-Precision Analog Front End Integrated in a 32bit Microcontroller for Industrial Sensing Applications. - Koji Yoichi; Sugako Otani; Kazutoshi Tsuda; Naoya Tokimoto; Hideki Kamegawa; Yoshihisa Satou; Shioto Tanaka; Hideki Otsu; Mitsuru Hiraki; Masao Ito; Mitsuya Fukazawa; Hiroyuki Kondo (A-SSCC, 2020)

9.7 Background Multi-Rate LMS Calibration Circuit for 15MHz-BW 74dB-DR CT 2-2 MASH ΔΣ ADC in 28nm CMOS. - Mitsuya Fukazawa; Takashi Oshima; Masaki Fujiwara; Katsuki Tateyama; Alsubaie Raed; Masao Ito; Tetsuya Matsumoto; Tetsuo Matsui (ISSCC, 2020)

A CT 2-2 MASH ΔΣ ADC With Multi-Rate LMS-Based Background Calibration and Input-Insensitive Quantization-Error Extraction. - Mitsuya Fukazawa; Takashi Oshima; Masaki Fujiwara; Katsuki Tateyama; Atsushi Ochi; Alsubaie Raed; Tetsuo Matsui (IEEE J. Solid State Circuits, 2021)

A 24-OSR to Simplify Anti-Aliasing Filter 2MHz-BW 83dB-DR 3rd-order DT-DSM using FIA-Based Integrator and Noise-Shaping SAR Combined Digital Noise-Coupling Quantizer. - Mitsuya Fukazawa; Tetsuo Matsui (VLSI Technology and Circuits, 2023)