Design for testability using register-transfer level partial scan selection. - Akira Motohara; Sadami Takeoka; Toshinori Hosokawa; Mitsuyasu Ohta; Yuji Takai; Michihiro Matsumoto; Michiaki Muraoka (ASP-DAC, 1995)

A Design for testability Method Using RTL Partitioning. - Toshinori Hosokawa; Kenichi Kawaguchi; Mitsuyasu Ohta; Michiaki Muraoka (Asian Test Symposium, 1996)

A Partial Scan Design Method Based on n-Fold Line-up Structures. - Toshinori Hosokawa; Toshihiro Hiraoka; Mitsuyasu Ohta; Michiaki Muraoka; Shigeo Kuninobu (Asian Test Symposium, 1997)

On validating data hold times for flip-flops in sequential circuits. - Sudhakar M. Reddy; Irith Pomeranz; Seiji Kajihara; Atsushi Murakami; Sadami Takeoka; Mitsuyasu Ohta (ITC, 2000)

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times. - Toshinori Hosokawa; Masayoshi Yoshimura; Mitsuyasu Ohta (ASP-DAC, 2001)

A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip. - Tetsuji Kishi; Mitsuyasu Ohta; Takashi Taniguchi; Hiroshi Kadota (Asian Test Symposium, 2001)

A Test Point Insertion Method to Reduce the Number of Test Patterns. - Masayoshi Yoshimura; Toshinori Hosokawa; Mitsuyasu Ohta (Asian Test Symposium, 2002)