Hierarchical top-down layout design method for VLSI chip. - Tohru Adachi; Hitoshi Kitazawa; Mitsuyoshi Nagatani; Tsuneta Sudo (DAC, 1982)

The Design of Dedicated 32-Bit Processors. - Shoji Horiguchi; Hiroshi Yoshimura; Mitsuyoshi Nagatani; Kennosuke Fukami (IEEE Des. Test, 1987)