A +10-dBm IIP3 SiGe mixer with IM3 cancellation technique. - Shoji Otaka; Mitsuyuki Ashida; Masato Ishii; Tetsuro Itakura (IEEE J. Solid State Circuits, 2004)

An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer. - Shusuke Kawai; Hiromitsu Aoyama; Rui Ito; Yutaka Shimizu; Mitsuyuki Ashida; Asuka Maki; Tomohiko Takeuchi; Hiroyuki Kobayashi; Go Urakawa; Hiroaki Hoshino; Shigehito Saigusa; Kazushi Koyama; et al. (ISSCC, 2018)

A 25.6Gb/s Uplink-Downlink Interface Employing PAM-4-Based 4-Channel Multiplexing and Cascaded CDR Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi (ISSCC, 2019)

A 56-Gb/s PAM4 Transceiver with False-Lock-Aware Locking Scheme for Mueller-Müller CDR. - Fumihiko Tachibana; Huy Cu Ngo; Go Urakawa; Takashi Toi; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Junji Wadatsumi; Hiroyuki Kobayashi; Jun Deguchi (ESSCIRC, 2022)

A 25.6-Gb/s Interface Employing PAM-4-Based Four-Channel Multiplexing and Cascaded Clock and Data Recovery Circuits in Ring Topology for High-Bandwidth and Large-Capacity Storage Systems. - Takashi Toi; Junji Wadatsumi; Hiroyuki Kobayashi; Yutaka Shimizu; Yuji Satoh; Makoto Morimoto; Rui Ito; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Go Urakawa; Jun Deguchi; et al. (IEEE J. Solid State Circuits, 2022)

A Mueller-Müller CDR with False-Lock-Aware Locking Scheme for a 56-Gb/s ADC-Based PAM4 Transceiver. - Fumihiko Tachibana; Huy Cu Ngo; Go Urakawa; Takashi Toi; Mitsuyuki Ashida; Yuta Tsubouchi; Mai Nozawa; Junji Wadatsumi; Hiroyuki Kobayashi; Jun Deguchi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024)