Energy-Efficient Acceleration of Deep Learning based Facial Recognition on RISC-V Processor. - Mitul Sudhirkumar Nagar; Vivek Chauhan; Karnav M. Chinchavde; Swati; Sat Patel; Pinalkumar Engineer (ISED, 2023)

A Memory Efficient Run-time Re-configurable Convolution IP Core for Deep Neural Networks Inference on FPGA Devices. - Swati; Ranajoy Sadhukhan; Mitul Sudhirkumar Nagar; Pinalkumar Engineer (iSES, 2023)

Memory-efficient Edge-based Non-Neural Face Recognition Algorithm on the Parallel Ultra-Low Power (PULP) Cluster. - Mitul Sudhirkumar Nagar; Sayantan Maiti; Rahul Kumar; Hiren K. Mewada; Pinalkumar Engineer (MCSoC, 2023)

Parallelizing Non-Neural ML Algorithm for Edge-based Face Recognition on Parallel Ultra-Low Power (PULP) Cluster. - Mitul Sudhirkumar Nagar; Rahul Kumar; Pinalkumar Engineer (MECO, 2023)

FPGA-Based High-Speed Energy-Efficient 32-Bit Fixed-Point MAC Architecture for DSP Application in IoT Edge Computing. - Mitul Sudhirkumar Nagar; Sohan H. Patel; Pinalkumar Engineer (J. Circuits Syst. Comput., 2024)

High-Speed Energy-Efficient Fixed-Point Signed Multipliers for FPGA-Based DSP Applications. - Mitul Sudhirkumar Nagar; Aditya Mathuriya; Sohan H. Patel; Pinalkumar Engineer (IEEE Embed. Syst. Lett., 2024)

Energy-efficient Non-Neural Face Recognition on the Multi-core RISC-V System. - Mitul Sudhirkumar Nagar; Pinalkumar Engineer (ISCAS, 2025)