500-Mb/s nonprecharged data bus for high-speed DRAM's. - Miyoshi Saito; Junji Ogawa; Hirotaka Tamura; Shigetoshi Wakayama; Hisakatsu Araki; Tsz-Shing Cheung; Kohtaroh Gotoh; Tadao Aikawa; Takaaki Suzuki; Masao Taguchi; Takeshi Imamura (IEEE J. Solid State Circuits, 1998)

Cyclic reconfiguration for pipelined applications on coarse-grain reconfigurable circuits. - Hisanori Fujisawa; Miyoshi Saito; Masaki Arai; Toshihiro Ozawa; Hideki Yoshizawa (FPT, 2004)

A new symbol timing synchronization for OFDM based WLANs. - Liang Zhou; Miyoshi Saito (PIMRC, 2004)

Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication. - Miyoshi Saito; Hisanori Fujisawa; Nobuo Ujiie; Hideki Yoshizawa (FPL, 2005)