Instruction-Vulnerability-Factor-Based Reliability Analysis Model for Program Memory. - Qingyu Chen; Li Chen 001; Haibin Wang; Longsheng Wu; Yuanqing Li; Xing Zhao; Mo Chen 008 (J. Electron. Test., 2016)

An SEU-Resilient SRAM Bitcell in 65-nm CMOS Technology. - Qingyu Chen; Haibin Wang; Li Chen 001; Lixiang Li 001; Xing Zhao; Rui Liu 011; Mo Chen 008; Xuantian Li (J. Electron. Test., 2016)

A 10-Transistor 65 nm SRAM Cell Tolerant to Single-Event Upsets. - Yuanqing Li; Lixiang Li 001; Yuan Ma; Li Chen 001; Rui Liu 011; Haibin Wang; Qiong Wu; Michael Newton; Mo Chen 008 (J. Electron. Test., 2016)

A Built-in Single Event Upsets Detector for Sequential Cells. - Yuanqing Li; Haibin Wang; Lixiang Li 001; Li Chen 001; Rui Liu 011; Mo Chen 008 (J. Electron. Test., 2016)

BPPT - Bulk potential protection technique for hardened sequentials. - Issam Nofal; Adrian Evans; Anlin He; Gang Guo; Yuanqing Li; Li Chen 001; Rui Liu 011; Haibin Wang; Mo Chen 008; Sang H. Baeg; Shi-Jie Wen; Richard Wong (IOLTS, 2017)

Modeling and analysis of single-event transient sensitivity of a 65 nm clock tree. - Yuanqing Li; Li Chen 001; Issam Nofal; Mo Chen 008; Haibin Wang; Rui Liu 011; Qingyu Chen; Milos Krstic; Shuting Shi; Gang Guo; Sang H. Baeg; Shi-Jie Wen; et al. (Microelectron. Reliab., 2018)

Single Event Upset Evaluation for a 28-nm FDSOI SRAM Type Buffer in an ARM Processor. - Shuting Shi; Rui Chen; Rui Liu 011; Mo Chen 008; Chen Shen; Xuantian Li; Haonan Tian; Li Chen 001 (J. Electron. Test., 2021)