Effect of nonlinearity in the CMFB circuit that uses the differential-difference amplifier. - Mo M. Zhang; Paul J. Hurst (ISCAS, 2006)

Gain-Error Calibration of a Pipelined ADC in an Adaptively Equalized Baseband Receiver. - Mo M. Zhang; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (IEEE Trans. Circuits Syst. II Express Briefs, 2009)

Calibration of pipelined ADC gain and memory errors in an adaptively equalized receiver. - Mo M. Zhang; Paul J. Hurst; Bernard C. Levy; Stephen H. Lewis (ISCAS, 2010)

26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS. - Massimo Brandolini; Young Shin; Karthik Raviprakash; Tao Wang 010; Rong Wu; Hemasundar Mohan Geddada; Yen-Jen Ko; Yen Ding; Chun-Sheng Huang; Wei-Ta Shih; Ming-Hung Hsieh; Wei-Te Chou; et al. (ISSCC, 2015)

A 5 GS/s 150 mW 10 b SHA-Less Pipelined/SAR Hybrid ADC for Direct-Sampling Systems in 28 nm CMOS. - Massimo Brandolini; Young Shin; Karthik Raviprakash; Tao Wang 010; Rong Wu; Hemasundar Mohan Geddada; Yen-Jen Ko; Yen Ding; Chun-Sheng Huang; Wei-Ta Shih; Ming-Hung Hsieh; Wei-Te Chou; et al. (IEEE J. Solid State Circuits, 2015)

An algorithmic ADC with greater than rail-to-rail input range and near-Vt supply. - Mo M. Zhang; Paul J. Hurst; Stephen H. Lewis (ISCAS, 2016)

27.6 A 4GS/s 13b pipelined ADC with capacitor and amplifier sharing in 16nm CMOS. - Jiangfeng Wu; Acer Wei-Te Chou; Tianwei Li; Rong Wu; Tao Wang 010; Giuseppe Cusmai; Sha-Ting Lin; Cheng-Hsun Yang; Greg Unruh; Sunny Raj Dommaraju; Mo M. Zhang; Po Tang Yang; et al. (ISSCC, 2016)